Abstract: A method, apparatus, and system for detecting DeepFake videos, includes an input device for inputting a potential DeepFake video, the input device inputs a sequence of video frames of the video, and processing circuitry. The processing circuitry detects faces frame by frame in the video to obtain consecutive face images, creates UV texture maps from the face images, inputs both face images and corresponding UV texture maps, extracts image feature maps, by a convolution neural network (CNN) backbone, from the input face images and corresponding UV texture maps and forms an input data structure, receives the input data structure, by a video transformer model that includes multiple encoders, and computes, by the video transformer model, a classification of the video as being Real or Fake. A display device plays back the potential DeepFake video and an indication that the video is Real or Fake.

Abstract: A switching circuit for a current source inverter includes a first inverter leg, a second inverter leg, and a controller. The first inverter leg includes a first reverse-voltage-blocking (RB) switch, a second RB switch, and a third RB switch that are connected in series between a first bus line and a second bus line. The second inverter leg includes a fourth RB switch, a fifth RB switch, and a sixth RB switch are connected in series between the first bus line and the second bus line. The controller is configured to control a switch between an on-state and an off-state for each RB switch. When in the on-state, a reverse voltage is blocked by a respective RB switch, and a current with a positive polarity is conducted through the respective RB switch. When in the off-state, a voltage and the current are blocked by the respective RB switch.

Abstract: A switching circuit for a current source inverter includes a first inverter leg, a second inverter leg, and a controller. The first inverter leg includes a first reverse-voltage-blocking (RB) switch, a second RB switch, and a third RB switch that are connected in series between a first bus line and a second bus line. The second inverter leg includes a fourth RB switch, a fifth RB switch, and a sixth RB switch are connected in series between the first bus line and the second bus line. The controller is configured to control a switch between an on-state and an off-state for each RB switch. When in the on-state, a reverse voltage is blocked by a respective RB switch, and a current with a positive polarity is conducted through the respective RB switch. When in the off-state, a voltage and the current are blocked by the respective RB switch.

Abstract: A switching circuit includes a reverse-voltage-blocking (RB) commutation switch, a first inverter leg, and a second inverter leg. The first inverter leg includes a first dual-gate bidirectional (DGBD) and a second DGBD switch connected in series. The second inverter leg includes a third and a fourth DGBD switch connected in series. A pair of the first DGBD switch, the second DGBD switch, the third DGBD switch, and the fourth DGBD switch that are in different inverter legs of the first inverter leg and the second inverter leg are configured to switch between a first DGBD on-state and a second DGBD on-state when in an inverting operating mode. A current with a positive or a negative polarity is conducted when in the first DGBD on-state. When in the second DGBD on-state, a reverse voltage is blocked by and a current with a positive polarity is conducted through the respective DGBD switch.

Abstract: A switching circuit includes a diode, a semiconductor switch, and a first bidirectional switch. The semiconductor switch is configured to conduct a first current from a second terminal to a third terminal of the semiconductor switch when a first on-state signal is sent to a first terminal of the semiconductor switch. An anode of the diode is connected to the second terminal of the semiconductor switch, and a cathode of the diode is connected to the third terminal of the semiconductor switch. The first bidirectional switch includes a first terminal, a second terminal connected to the anode of the diode, and a third terminal and is configured to conduct a second current from the second terminal to the third terminal or from the third terminal to the second terminal when a second on-state signal is sent to the first terminal of the first bidirectional switch.

Abstract: A switching circuit includes a diode, a semiconductor switch, and a first bidirectional switch. The semiconductor switch is configured to conduct a first current from a second terminal to a third terminal of the semiconductor switch when a first on-state signal is sent to a first terminal of the semiconductor switch. An anode of the diode is connected to the second terminal of the semiconductor switch, and a cathode of the diode is connected to the third terminal of the semiconductor switch. The first bidirectional switch includes a first terminal, a second terminal connected to the anode of the diode, and a third terminal and is configured to conduct a second current from the second terminal to the third terminal or from the third terminal to the second terminal when a second on-state signal is sent to the first terminal of the first bidirectional switch.

Abstract: This disclosure relates to improved techniques for performing image segmentation functions using neural network architectures. The neural network architecture integrates an edge guidance module and object segmentation network into a single framework for detecting target objects and performing segmentation functions. The neural network architecture can be trained to generate edge-attention representations that preserve the edge information included in images. The neural network architecture can be trained to generate multi-scale feature information that preserves and enhances object-level feature information included in images. The edge-attention representations and multi-scale feature information can be fused to generate segmentation results that identify target object boundaries with increased accuracy.

Abstract: An apparatus for collecting and controlling a temperature is closed, it comprises a temperature collecting unit (1), a temperature collecting path (2) and a temperature controlling unit (3). The temperature collecting path (2) comprises a fast sensing path (20) and a slow sensing path (22). The fast sensing path (20) is connected to temperature sensing spots of a device and is used for obtaining temperatures of the temperature sensing spots of the device in a first predefined period. The slow sensing path (22) is connected to functional units (5) of the device and is used for obtaining temperatures of the functional units in a second predefined period. The second predefined period is greater than the first predefined period.

Abstract: An apparatus for collecting and controlling a temperature is closed, it comprises a temperature collecting unit (1), a temperature collecting path (2) and a temperature controlling unit (3). The temperature collecting path (2) comprises a fast sensing path (20) and a slow sensing path (22). The fast sensing path (20) is connected to temperature sensing spots of a device and is used for obtaining temperatures of the temperature sensing spots of the device in a first predefined period. The slow sensing path (22) is connected to functional units (5) of the device and is used for obtaining temperatures of the functional units in a second predefined period. The second predefined period is greater than the first predefined period.