Abstract: A circuit and method for simulating real-time reconfigurable general-purpose memristor, nonlinear m-order polynomial fitting of mathematical model of a memristor is performed by using McLaughlin formula. m is related to the amplitude and frequency of an input signal and the fitting accuracy, thus the mathematical model of a memristor can be easily and quickly adapted by updating the polynomial order, the polynomial coefficients and the FPGA system clock cycle. Based on the FPGA, a system state variable generation module, a FIFO, a output module are used to obtain an output signal y[n]. the detailed steps of signal processing and displaying are given to obtain a display of a pinched hysteresis loop and a waveform display of time-domain. Simulation of high frequency memristor by setting polynomial coefficients can be obtained. Meanwhile, this is built based on FPGA, adopt digital circuit to simulates a reconfigurable general-purpose memristor, and experimental accuracy is enhanced.

Abstract: A random transient power test signal generator based on three-dimensional memristive discrete map, which utilizes a three-dimensional parallel bi-memristor Logistic map module to generate two pseudo-random sequences, and based on the two pseudo-random sequences, uses two waveform output modules to generate a transient voltage signal and a transient current signal respectively, thus the random transient power testing signal is obtained.

Abstract: The present invention provides a system for data mapping and storing in digital three-dimensional oscilloscope, wherein the fixed coefficients, which are calculated according the parameters and settings of a digital oscilloscope, are stored into a fixed coefficient memory CO RAM, the fixed coefficients are outputted to N fractional operation units through N?1 D flip-flop delay units to multiply with the acquired data x(n) and then be accumulated, thus N fractional calculus results are obtained. In this way, N fractional calculus results can be obtained by performing L/N fractional calculus operations. N fractional calculus results are sent to a signal processing and display module, in which they are converted into a display data through a drawing thread, and the display data are sent to LCD for displaying, thus the fractional calculus operation and display of a input signal in a digital oscilloscope is realized.

Abstract: A system maps and stores data in digital three-dimensional oscilloscope, wherein an ADC module has four ADC submodules. Four acquired waveform data are sent to an extraction module, and buffered in a FIFO module. When a trigger signal arrives, FIFO module outputs four extracted waveform data to a mapping address calculation module for calculating a mapping address and a RAM serial number for each point data, and the waveform data comparison and control module performs the reading and writing control of the 4×N dual port RAMs. When mapping number reaches a frame number, the RAM array module outputs its waveform probability values to the upper computer module to convert each value into RBG values, and the display module displays the waveforms of input signals of four channels on a screen according the RBG values.

Abstract: A system maps and stores data in digital three-dimensional oscilloscope, wherein an ADC module has four ADC submodules. Four acquired waveform data are sent to an extraction module, and buffered in a FIFO module. When a trigger signal arrives, FIFO module outputs four extracted waveform data to a mapping address calculation module for calculating a mapping address and a RAM serial number for each point data, and the waveform data comparison and control module performs the reading and writing control of the 4×N dual port RAMs. When mapping number reaches a frame number, the RAM array module outputs its waveform probability values to the upper computer module to convert each value into RBG values, and the display module displays the waveforms of input signals of four channels on a screen according the RBG values.