Abstract: A flip chip package unit and associated packaging method. The flip chip package unit may include an integrated circuit (“IC”) die having a plurality of metal pillars formed on its first surface and attached to a rewiring substrate with the first surface of the IC die facing to the rewiring substrate, an under-fill material filling gaps between the first surface of the IC die and the rewiring substrate, and a back protective film attached to a second surface of the IC die. The back protective film may have good UV sensitivity to change from non-solid to solid after UV irradiation while maintaining its viscosity with the IC die not reduced after UV irradiation. The back protective film may be uneasy to deform and to peel off from the IC die and can provide physical protection and effective heat dissipation path to the IC die.

Abstract: A power module, having a bottom substrate, a device substrate arranged on the bottom substrate and an inductor assembly arranged on the device substrate. The device substrate having a first power device chip and a second power device chip embedded within the device substrate. Each power device chip has a first surface and a second surface. The first surface of each power device chip is covered by a top heat layer, and the second surface of each power device chip has a plurality of pins or pads exposed on the second surface of the device substrate, and connected to the bottom substrate.

Abstract: Provided are a chitin-based superabsorbent materials and method of preparation thereof. The superabsorbent material comprises chitin crosslinked by an epoxy crosslinker, and guanidine attached to the crosslinked chitin. The preparation method includes dissolving chitin in an aqueous solvent to form a solution; reacting the dissolved chitin with an epoxy crosslinker and guanidine, or a salt thereof, thereby forming a hydrogel; and drying the hydrogel.

Abstract: A flip chip package unit and associated packaging method. The flip chip package unit may include an integrated circuit (“IC”) die having a plurality of metal pillars formed on its first surface and attached to a rewiring substrate with the first surface of the IC die facing to the rewiring substrate, an under-fill material filling gaps between the first surface of the IC die and the rewiring substrate, and a thermal conductive protection film covering or overlaying and directly contacting with the entire second die surface and a first portion of sidewalls of the IC die. The thermal conductive protection film may have good thermal conductivity, uneasy to fall off from the IC die and can provide physical protection, electromagnetic interference protection and effective heat dissipation path to the IC die.

Abstract: A pneumatic-driven fluidic cartridge and systems and methods for operating the same. The cartridge includes a substrate layer, an actuator layer, and an elastic layer. A fluid channel formed in a surface of the substrate layer includes a first chamber and a second chamber separated by a block section. The actuator layer includes a lever positioned to extend across the block section. The elastic layer is positioned between the substrate layer and the actuator layer. The lever applies a force to the elastic layer restricts fluid flow from the first chamber to the second chamber and is configured to bend outwardly opening a channel between the block section and the elastic layer exceeds the first threshold pressure.

Abstract: A substrate includes a first dielectric layer having a first surface and a second surface. The first dielectric layer includes a plurality of first conductive vias and a plurality of second conductive vias. These two kinds of conductive vias are formed to penetrate the first dielectric layer and have different orientations for reduce warpage of the substrate.

Abstract: An IC package structure including an array of package units formed into a panel-shaped package units array. Each package unit has a continuous and closed metal wall surrounding the periphery of the package unit and at least one IC chip/IC die disposed in the package unit, and wherein each IC chip/IC die has a top surface and a back surface opposite to the top surface. A panel-shaped metal layer corresponding to the panel-shaped package units array can be formed on entire back side of the IC package structure and bonded to the metal wall of each package unit, wherein the back side of the IC package structure refers to the side to which the back surface of each IC chip/IC die is facing.

Abstract: A panel-shaped metal wall grids array for panel level IC packaging and associated manufacturing method. Each metal wall grid in the metal wall grids array has a continuous and closed metal wall of a predetermined wall height. The metal wall grids are connected to form a monolithic panel through a plurality of metal connecting portions. When the panel-shaped metal wall grids array is used for panel level IC packaging, at least one IC chip/IC die is disposed in each metal wall grid with a top surface of each IC chip/IC die facing downwards, and a panel-shaped metal layer matching with the panel-shaped wall grids array may be further formed on the entire back side of the panel-shaped metal wall grids array so that the panel-shaped metal layer is bonded to the metal wall of each metal wall grid.

Abstract: An IC package structure and an IC package unit are disclosed. The IC package includes an array of metal wall grids formed into a panel, each one of the metal wall grids having a continuous and closed metal wall to surround an IC package unit with at least one IC chip/IC die disposed therein. Each IC chip/IC die has a top surface with a plurality of metal pads formed thereon. A panel-shaped metal layer is formed on entire back side of the panel of the array of metal wall grids and bonded to the metal wall of each metal wall grid. A panel-shaped rewiring substrate having a plurality of metal pillars is connected to each IC chip/IC die with each one of the plurality of metal pillars soldered with a corresponding one of the plurality of metal pads.

Abstract: A flip chip package unit and associated packaging method. The flip chip package unit may include an integrated circuit (“IC”) die having a plurality of metal pillars formed on its first surface and attached to a rewiring substrate with the first surface of the IC die facing to the rewiring substrate, an under-fill material filling gaps between the first surface of the IC die and the rewiring substrate, and a back protective film attached to a second surface of the IC die. The back protective film may have good UV sensitivity to change from non-solid to solid after UV irradiation while maintaining its viscosity with the IC die not reduced after UV irradiation. The back protective film may be uneasy to deform and to peel off from the IC die and can provide physical protection and effective heat dissipation path to the IC die.

Abstract: A flip chip package unit and associated packaging method. The flip chip package unit may include an integrated circuit (“IC”) die having a plurality of metal pillars formed on its first surface and attached to a rewiring substrate with the first surface of the IC die facing to the rewiring substrate, an under-fill material filling gaps between the first surface of the IC die and the rewiring substrate, and a thermal conductive protection film covering or overlaying and directly contacting with the entire second die surface and a first portion of sidewalls of the IC die. The thermal conductive protection film may have good thermal conductivity, uneasy to fall off from the IC die and can provide physical protection, electromagnetic interference protection and effective heat dissipation path to the IC die.

Abstract: A system, computer program product, and method are provided for entity linking in a logical neural network (LNN). A set of features are generated for one or more entity-mention pairs in an annotated dataset. The generated set of features is evaluated against an entity linking LNN rule template having one or more logically connected rules and corresponding connective weights organized in a tree structure. An artificial neural network is leveraged along with a corresponding machine learning algorithm to learn the connective weights. The connective weights associated with the logically connected rules are selectively updated and a learned model is generated with learned thresholds and the learned weights for the logically connected rules.

Abstract: An IC package structure and associated packaging method. The IC package structure may include an array of package units formed into a panel, wherein each one of the array of package units comprises at least one IC chip/IC die. Each IC chip/IC die may be at least partially covered and wrapped by an encapsulation layer having one or more openings to expose entire or at least a portion of a back surface of each IC chip/IC die. A metal layer may be electroplated on entire back side of the IC package structure to fill the openings in the encapsulation layer so that the metal layer is in direct contact with the exposed portions of the back surface of each IC chip/IC die.

Abstract: Embodiments of the present disclosure disclose a method and apparatus for recommending a video. A specific implementation of the method includes: finding a recommended video corresponding to a target video from all candidate videos based on similarities of content characteristics of the videos, the target video being a video to be played on a terminal of a user; and sending play information of the recommended video corresponding to the target video to the terminal of the user. The method finds a video similar on video content to the target video that the user desires to view based on the content characteristic of the video, and recommends the video similar on video content to the target video that the user desires to view to the user.

Abstract: A panel-shaped metal wall grids array for panel level IC packaging and associated manufacturing method. Each metal wall grid in the metal wall grids array has a continuous and closed metal wall of a predetermined wall height. The metal wall grids are connected to form a monolithic panel through a plurality of metal connecting portions.

Abstract: An IC package structure and an IC package unit are disclosed. The IC package includes an array of metal wall grids formed into a panel, each one of the metal wall grids having a continuous and closed metal wall to surround an IC package unit with at least one IC chip/IC die disposed therein. Each IC chip/IC die has a top surface with a plurality of metal pads formed thereon. A panel-shaped metal layer is formed on entire back side of the panel of the array of metal wall grids and bonded to the metal wall of each metal wall grid. A panel-shaped rewiring substrate having a plurality of metal pillars is connected to each IC chip/IC die with each one of the plurality of metal pillars soldered with a corresponding one of the plurality of metal pads.

Abstract: An IC package structure including an array of package units formed into a panel-shaped package units array. Each package unit has a continuous and closed metal wall surrounding the periphery of the package unit and at least one IC chip/IC die disposed in the package unit, and wherein each IC chip/IC die has a top surface and a back surface opposite to the top surface. A panel-shaped metal layer corresponding to the panel-shaped package units array can be formed on entire back side of the IC package structure and bonded to the metal wall of each package unit, wherein the back side of the IC package structure refers to the side to which the back surface of each IC chip/IC die is facing.

Abstract: An integrated circuit (IC) chip includes a copper structure with an intermetallic coating on the surface. The IC chip includes a substrate with an integrated circuit. A metal pad electrically connects to the integrated circuit. The copper structure electrically connects to the metal pad. A solder bump is disposed on the copper structure. The surface of the copper structure has a coating of intermetallic. The copper structure can be a redistribution layer and a copper pillar that is disposed on the redistribution layer.

Abstract: Embodiments of the present disclosure disclose a method and apparatus for recommending a video. A specific implementation of the method includes: finding a recommended video corresponding to a target video from all candidate videos based on similarities of content characteristics of the videos, the target video being a video to be played on a terminal of a user; and sending play information of the recommended video corresponding to the target video to the terminal of the user. The method finds a video similar on video content to the target video that the user desires to view based on the content characteristic of the video, and recommends the video similar on video content to the target video that the user desires to view to the user.

Abstract: A semiconductor device reducing parasitic loop inductance of system for the switching converter. The semiconductor device has an input voltage pin, a ground reference pin, a switching pin, and a semiconductor die, wherein the semiconductor die comprises a high-side power switch and a low-side power switch and a metal connection. The metal connection directly connects the high-side power switch and the first terminal of the low-side power switch, and is along and proximity to an edge of the semiconductor device to which the input voltage pin is distributed.