Patents by Inventor Hang-Shing Ma

Hang-Shing Ma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • 3D interconnect structure comprising through-silicon vias combined with fine pitch backside metal redistribution lines fabricated using a dual damascene type approach
    Patent number: 9530740
    Abstract: A 3D interconnect structure and method of manufacture are described in which a through-silicon vias (TSVs) and metal redistribution layers (RDLs) are formed using a dual damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and etch stop layer during the process flow.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: December 27, 2016
    Assignee: Intel Corporation
    Inventors: Kevin J. Lee, Mark T. Bohr, Andrew W. Yeoh, Christopher M. Pelto, Hiten Kothari, Seshu V. Sattiraju, Hang-Shing Ma
  • 3D interconnect structure comprising fine pitch single damascene backside metal redistribution lines combined with through-silicon vias
    Patent number: 9449913
    Abstract: A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a single damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: September 20, 2016
    Assignee: Intel Corporation
    Inventors: Kevin J. Lee, Mark T. Bohr, Andrew W. Yeoh, Christopher M. Pelto, Hiten Kothari, Seshu V. Sattiraju, Hang-Shing Ma
  • 3D INTERCONNECT STRUCTURE COMPRISING THROUGH-SILICON VIAS COMBINED WITH FINE PITCH BACKSIDE METAL REDISTRIBUTION LINES FABRICATED USING A DUAL DAMASCENE TYPE APPROACH
    Publication number: 20150364425
    Abstract: A 3D interconnect structure and method of manufacture are described in which a through-silicon vias (TSVs) and metal redistribution layers (RDLs) are formed using a dual damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and etch stop layer during the process flow.
    Type: Application
    Filed: August 26, 2015
    Publication date: December 17, 2015
    Inventors: Kevin J. Lee, Mark T. BOHR, Andrew W. YEOH, Christopher M. PELTO, Hiten KOTHARI, Seshu V. SATTIRAJU, Hang-Shing MA
  • 3D interconnect structure comprising through-silicon vias combined with fine pitch backside metal redistribution lines fabricated using a dual damascene type approach
    Patent number: 9142510
    Abstract: A 3D interconnect structure and method of manufacture are described in which a through-silicon vias (TSVs) and metal redistribution layers (RDLs) are formed using a dual damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and etch stop layer during the process flow.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: September 22, 2015
    Assignee: Intel Corporation
    Inventors: Kevin J. Lee, Mark T. Bohr, Andrew W. Yeoh, Christopher M. Pelto, Hiten Kothari, Seshu V. Sattiraju, Hang-Shing Ma
  • 3D INTERCONNECT STRUCTURE COMPRISING THROUGH-SILICON VIAS COMBINED WITH FINE PITCH BACKSIDE METAL REDISTRIBUTION LINES FABRICATED USING A DUAL DAMASCENE TYPE APPROACH
    Publication number: 20130285257
    Abstract: A 3D interconnect structure and method of manufacture are described in which a through-silicon vias (TSVs) and metal redistribution layers (RDLs) are formed using a dual damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and etch stop layer during the process flow.
    Type: Application
    Filed: October 28, 2011
    Publication date: October 31, 2013
    Inventors: Kevin J. Lee, Mark T. Bohr, Andrew W. Yeoh, Christopher M. Pelto, Hiten Kothari, Seshu V. Sattiraju, Hang-Shing Ma
  • 3D INTERCONNECT STRUCTURE COMPRISING FINE PITCH SINGLE DAMASCENE BACKSIDE METAL REDISTRIBUTION LINES COMBINED WITH THROUGH-SILICON VIAS
    Publication number: 20130256910
    Abstract: A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a single damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow.
    Type: Application
    Filed: October 28, 2011
    Publication date: October 3, 2013
    Inventors: Kevin J. Lee, Mark T. Bohr, Andrew W. Yeoh, Christopher M. Pelto, Hiten Kothari, Seshu V. Sattiraju, Hang-Shing Ma