Abstract: A system and method for improved cache performance is disclosed. In one embodiment, cache coherency schemes are categorized by whether or not they are capable of write-back caching. A signal may convey this information among the processors, allowing them to inhibit snooping in certain cases. In another embodiment, backoff signals may be exchanged among the processors, permitting them to inhibit certain unnecessary data transfers on a system bus.

Abstract: A method and apparatus for fixed latency subtractive decoding. The subtractive decoding device speculatively acknowledges a bus transaction within a fixed time period that is the same as the time period for positive decoding. Pipelining of a new bus transaction may therefore be accomplished each new time period. A bus transaction may be retried if no acknowledgement occurs within the fixed time period.

Abstract: A method and apparatus for optimizing line writes in cache coherent systems. A new cache line may be allocated without loading data to fill the new cache line when a store buffer coalesces enough stores to fill the cache line. Data may be loaded to fill the line if an insufficient number of stores are coalesced to fill the entire cache line. The cache line may be allocated by initiating a read and invalidate request and asserting a back-off signal to cancel the read if there is an indication that the coalesced stores will fill the cache line.

Abstract: A system includes a bus shared by a plurality of devices and a logic circuit adapted to segment the bus into a plurality of portions. In one embodiment of the present invention, the system may include a plurality of devices and a first multiplexer logic circuit adapted to select signals from the plurality of devices. A second multiplexer circuit may receive the selected signals from the first multiplexer circuit and transmit the selected signals to chosen ones of the plurality of devices.

Abstract: A system and method for checking and correcting soft errors in a next instruction pointer is described. In one embodiment, a parity bit is generated for a next instruction pointer that is produced in a front end of a processor. The next instruction pointer and the parity bit are staged from the front end of the processor to a back end of the processor. Another next instruction pointer is generated in the back end of the processor when an instruction corresponding to the next instruction pointer generated in the front end executes. The next instruction pointer generated in the back end is also parity protected. The next instruction pointer generated in the front end is checked for a parity error. The next instruction pointer generated in the back end is also checked for the parity error. Finally, both next instruction pointers are compared to determine if both are equal.

Abstract: A conditional read and invalidate operation for use in coherent multiprocessor systems is disclosed. A conditional read and invalidate request may be sent via an interconnection network from a first processor that requires exclusive access to a cache block to a second processor that requires exclusive access to the cache block. Data associated with the cache block may be sent from the second processor to the first processor in response to the conditional read and invalidate request and a determination that the cache block is associated with a state of a cache coherency protocol.

Abstract: Methods and apparatus for cache-to-cache block transfers (i.e., intervention) when the state of the transferred block is in a non-modified state (e.g., “exclusive” or “shared”) are provided. In one embodiment, a first cache holds the memory block in an “exclusive” state prior to the transfer. When a processor associated with a second cache attempts to read the block from a main memory, the first cache intervenes and supplies the block to the second cache. The state of the block in the first cache changes from “exclusive” to “shared.” In another embodiment, a processor associated with a third cache attempts to read the block from the main memory while the first cache and the second both hold the block in the “shared” state. Either the first cache or the second cache wins an arbitration and supplies the block to the third cache. In both embodiments, communications with main memory and power consumption are reduced.

Abstract: An processor includes first and second execution cores that operate in an FRC mode, an FRC check unit to compare results from the first and second execution cores, and an error check unit to detect recoverable errors in the first and second cores. The FRC check unit temporarily stores results from the first or second core, and a timer is activated if a mismatch is detected. If the error detector detects a recoverable error before the timer interval expires, a recovery routine is activated. If the timer interval expires first, a reset routine is activated.

Abstract: A processor includes one or more execution cores, each execution core having an associated scan chain to provide data to a set of voltage nodes of the core. A reset module drives a data pattern onto the scan line, responsive to a reset event. The data pattern places the set of voltage nodes of each execution core into specified logic states. For a processor including multiple execution cores configured to operate in an FRC mode, identical data patterns are driven onto the scan chains to reduce indeterminacy in the reset machine state of the processor.

Abstract: A portion of an integrated circuit (IC) is operated at a high operating frequency while the IC communicates at a bus frequency during a first period of time. A throttle signal is sent to the IC, and in response, the high operating frequency is reduced to a low operating frequency. The portion of the IC is then operated at the low operating frequency while the IC communicates at the bus frequency during a second period of time. Alternatively, the IC, in response to the throttle signal, stalls at least a portion of a pipeline or issues no-ops to the pipeline.

Abstract: A technique to detect and correct corruption of instructions by soft errors. A parity bit is propagated with an instruction through the instruction flow path and checked at selected places. When a parity error is detected, a replay circuit is used to perform a replay to reload the instruction to remove the corrupted instruction.

Abstract: An apparatus and method for testing multi-core processors by simultaneously testing each of the multiple cores. The full vector of test results for a master core is sent to the test equipment for evaluation while the test results for the slave(s) are logically compared to those of the master, with the result of the comparison reduced to one or more bits.

Abstract: A head suspension assembly for a hard disk drive data storage device which prevents contact between the head portion of the mechanism and the surface of the data storage media. An arm member includes a head assembly secured to one end and a bushing at the other end for engaging a rotatable positioning shaft. The arm member applies a resilient beam loading force to urge the arm member away from the media, and includes an aerodynamic airfoil that interacts with the air flow adjacent to the media surface to oppose the beam loading force and move the arm member toward the media to a proper flying height. When the disk is spinning, the negative lift of the airfoil opposes the resilient loading of the arm member and urges the arm member closer to the surface of the rotating media. As the head approaches the rotating surface, the positive lift of the air bearing counterbalances the negative lift from the airfoil such that a dynamic equilibrium is established at a predetermined flying height.

Abstract: A method is provided for removing paraffin deposits from the interior of a hydrocarbon transmission conduit, such as a subsea pipeline. The method comprises the steps of introducing into an isolated length of the conduit containing the paraffin a pre-determinable amount of an emulsified mixture of an aqueous solution and a hydrocarbon solution. The composition used in the method incorporates an aqueous solution which comprises in-situ nitrogen-generating components together with a sufficient amount of a buffered pH adjuster to produce a buffered pH value for the aqueous solution to abate the time of the reaction rate of the nitrogen-generating components to a level permitting introduction of the components into the isolated length prior to completion of any significant portion of the reactin required to effect temperature melting of the paraffin deposits. In a preferred form, a crystalline modifier may be incorporated into the hydrocarbon solution.