Abstract: The present invention provides an access mechanism for the testing of modules within an integrated circuit. A test access architecture is implemented which allows embedded testing of reusable modules with reusable test vectors regardless of the configuration of the integrated circuit. Modules within the integrated circuit may receive previously developed test vectors directly from a test input bus without having to propagate them through intervening modules. The module is controlled to accept as input either normal system inputs or the previously developed test vectors by logic circuits embedded within each module. The module's output is routed by a test output bus for dynamically observing test results at the system pins.