Abstract: A method, system, and storage medium for increasing the efficiency of integrated circuit (IC) manufacture by improvements in manufacturing equipment usage are provided. Process tools are assigned to one of three operating states: up, down, or conditional. In the up state, process tools are available for manufacturing. After certain manufacturing steps, the quality of the ICs being made upon wafers is evaluated. If potentially defective ICs are found, process tools that have processed the wafer may be placed in the conditional state. In this state, process tools are allowed to continue manufacturing, albeit only for a limited period. The conditional state gives personnel time to determine which process tool is responsible for the defective product. The responsible process tool is then placed in the down state while all others are placed back in the up state. Once the problem with the process tool in the down state is presumably repaired, it is placed in the conditional state.

Abstract: The present invention is directed to a method for manufacturing semiconductor devices. The method generally comprises forming a plurality of process layers on a wafer 14. The wafer has an edge region 20 with a number of defects 26 existing thereon. Thereafter, the method comprises removing all or a substantial portion of the defects 26 on the edge region 20 of the wafer 14.