Patents by Inventor HANGEOL LEE

HANGEOL LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11462610
    Abstract: Capacitor forming methods may include sequentially forming a first mold layer, a first support material layer, and a second mold layer on a substrate, forming a mask pattern on the second mold layer, forming a recess in the second mold layer, the first support material layer, and the first mold layer using the mask pattern as a mask, forming a lower electrode in the recess, removing the mask pattern by a dry cleaning process, reducing a width of an upper portion of the lower electrode, removing the first mold layer, forming a dielectric layer on a surface of the lower electrode, and forming an upper electrode on the dielectric layer.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: October 4, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoonyoung Choi, Byunghyun Lee, Byeongjoo Ku, Seungjin Kim, Sangjae Park, Jinwoo Bae, Hangeol Lee, Bowo Choi, Hyunsil Hong
  • Patent number: 11152368
    Abstract: A semiconductor device includes a substrate, a storage node electrode disposed on the substrate, a dielectric layer at least partially covering the storage node electrode, and a plate electrode dispose on the dielectric layer. The storage node electrode has a pillar shape, and includes a seam disposed therein. The storage node electrode includes a concave side surface disposed at a higher level than the seam.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: October 19, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yoonyoung Choi, Byunghyun Lee, Seungjin Kim, Byeongjoo Ku, Sangjae Park, Hangeol Lee
  • Publication number: 20210151439
    Abstract: A semiconductor device includes a substrate, a storage node electrode disposed on the substrate, a dielectric layer at least partially covering the storage node electrode, and a plate electrode dispose on the dielectric layer. The storage node electrode has a pillar shape, and includes a seam disposed therein. The storage node electrode includes a concave side surface disposed at a higher level than the seam.
    Type: Application
    Filed: June 23, 2020
    Publication date: May 20, 2021
    Inventors: YOONYOUNG CHOI, Byunghyun Lee, Seungjin Kim, Byeongjoo Ku, Sangjae Park, Hangeol Lee
  • Publication number: 20210036101
    Abstract: Capacitor forming methods may include sequentially forming a first mold layer, a first support material layer, and a second mold layer on a substrate, forming a mask pattern on the second mold layer, forming a recess in the second mold layer, the first support material layer, and the first mold layer using the mask pattern as a mask, forming a lower electrode in the recess, removing the mask pattern by a dry cleaning process, reducing a width of an upper portion of the lower electrode, removing the first mold layer, forming a dielectric layer on a surface of the lower electrode, and forming an upper electrode on the dielectric layer.
    Type: Application
    Filed: July 17, 2020
    Publication date: February 4, 2021
    Inventors: YOONYOUNG CHOI, BYUNGHYUN LEE, BYEONGJOO KU, SEUNGJIN KIM, SANGJAE PARK, JINWOO BAE, HANGEOL LEE, BOWO CHOI, HYUNSIL HONG