Abstract: The present disclosure shows ways to use multiple “integrated voltage regulator (IVR) units” to offer IVRs that can cover a wide range of specifications without having to design separate IVRs for different specifications. Instead of designing separate IVRs and paying for separate mask sets for IVRs targeting different specifications (e.g., different design and mask sets for 1 A IVR, 5 A IVR), the disclosed embodiments present ways to design and fabricate large numbers of the same unit IVRs (e.g., 1 A IVR) and decide how many of them to use post-fabrication to deliver different current specifications (e.g., use five 1 A unit IVRs for 5 A, use ten 1 A unit IVRs for 10 A). These disclosed embodiments reduce the mask cost of fabricating IVRs for different specifications and reduce design time by focusing on a single unit IVR.

Abstract: The present disclosure shows a hybrid regulator topology that can be more easily integrated and that can maintain high efficiency across a wide output and input voltage range, even with a small inductor. The hybrid regulator topology can include two types of regulators: a flying switched-inductor regulator and a step-down regulator that divides the input voltage into an M/N fraction of the input voltage. The disclosed embodiments of the hybrid regulator topology can reduce the capacitive loss of the flying switched-inductor regulator by limiting the voltage swing across the switches in the flying switched-inductor regulator. The disclosed embodiments of the hybrid regulator topology can reduce the inductor resistive loss of the flying switched-inductor regulator by operating the flying switched-inductor regulator at a high switching frequency and with a small amount of current flow through the inductor.

Abstract: The present disclosure provides an asymmetric switching capacitor regulator that is capable of providing an output voltage, covering a wide voltage range, with a high efficiency. The disclosed switching capacitor regulator is configured to generate a wide range of an output voltage by differentiating a voltage across one or more switching capacitors from a voltage across the rest of the switching capacitors in the switching capacitor regulator.

Abstract: The present disclosure provides an asymmetric switching capacitor regulator that is capable of providing an output voltage, covering a wide voltage range, with a high efficiency. The disclosed switching capacitor regulator is configured to generate a wide range of an output voltage by differentiating a voltage across one or more switching capacitors from a voltage across the rest of the switching capacitors in the switching capacitor regulator.

Abstract: The present disclosure shows a reconfigurable Dickson Star SC regulator that can support multiple conversion ratios by reconfiguring between various modes. The reconfigurable Dickson Star SC regulator is designed to reduce the number of redundant capacitors by reusing capacitors and switches across multiple modes of operation (across multiple conversion ratios). The present disclosure also shows a hybrid (e.g., two-stage) voltage regulator.

Abstract: The present disclosure shows a reconfigurable Dickson Star SC regulator that can support multiple conversion ratios by reconfiguring between various modes. The reconfigurable Dickson Star SC regulator is designed to reduce the number of redundant capacitors by reusing capacitors and switches across multiple modes of operation (across multiple conversion ratios). The present disclosure also shows a hybrid (e.g., two-stage) voltage regulator.

Abstract: The present disclosure includes a feedback system that can control hybrid regulator topologies that have multiple converters or regulators connected in series. The hybrid regulator can include at least two regulators: a switched inductor regulator and a switched-capacitor regulator. The disclosed embodiments of the feedback system can simplify feedback design for the hybrid regulator that can include multiple converter stages. These disclosed embodiments can control the feedback to improve the efficiency of a hybrid regulator.

Abstract: The present disclosure includes a feedback system that can control hybrid regulator topologies that have multiple converters or regulators connected in series. The hybrid regulator can include at least two regulators: a switched inductor regulator and a switched-capacitor regulator. The disclosed embodiments of the feedback system can simplify feedback design for the hybrid regulator that can include multiple converter stages. These disclosed embodiments can control the feedback to improve the efficiency of a hybrid regulator.

Abstract: A minimally invasive, wireless ECoG microsystem is provided for chronic and stable neural recording. Wireless powering and readout are combined with a dual rectification power management circuitry to simultaneously power to and transmit a continuous stream of data from an implant with a micro ECoG array and an external reader. Area and power reduction techniques in the baseband and wireless subsystem result in over 10×IC area reduction with a simultaneous 3× improvement in power efficiency, enabling a minimally invasive platform for 64-channel recording. The low power consumption of the IC, together with the antenna integration strategy, enables remote powering at 3× below established safety limits, while the small size and flexibility of the implant minimizes the foreign body response.

Abstract: The present disclosure provides an asymmetric switching capacitor regulator that is capable of providing an output voltage, covering a wide voltage range, with a high efficiency. The disclosed switching capacitor regulator is configured to generate a wide range of an output voltage by differentiating a voltage across one or more switching capacitors from a voltage across the rest of the switching capacitors in the switching capacitor regulator.

Abstract: The present disclosure shows a hybrid regulator topology that can be more easily integrated and that can maintain high efficiency across a wide output and input voltage range, even with a small inductor. The hybrid regulator topology can include two types of regulators: a flying switched-inductor regulator and a step-down regulator that divides the input voltage into an M/N fraction of the input voltage. The disclosed embodiments of the hybrid regulator topology can reduce the capacitive loss of the flying switched-inductor regulator by limiting the voltage swing across the switches in the flying switched-inductor regulator. The disclosed embodiments of the hybrid regulator topology can reduce the inductor resistive loss of the flying switched-inductor regulator by operating the flying switched-inductor regulator at a high switching frequency and with a small amount of current flow through the inductor.

Abstract: The present disclosure includes a feedback system that can control hybrid regulator topologies that have multiple converters or regulators connected in series. The hybrid regulator can include at least two regulators: a switched inductor regulator and a switched-capacitor regulator. The disclosed embodiments of the feedback system can simplify feedback design for the hybrid regulator that can include multiple converter stages. These disclosed embodiments can control the feedback to improve the efficiency of a hybrid regulator.

Abstract: The present disclosure shows ways to use multiple “integrated voltage regulator (IVR) units” to offer IVRs that can cover a wide range of specifications without having to design separate IVRs for different specifications. Instead of designing separate IVRs and paying for separate mask sets for IVRs targeting different specifications (e.g., different design and mask sets for 1 A IVR, 5 A IVR), the disclosed embodiments present ways to design and fabricate large numbers of the same unit IVRs (e.g., 1 A IVR) and decide how many of them to use post-fabrication to deliver different current specifications (e.g., use five 1 A unit IVRs for 5 A, use ten 1 A unit IVRs for 10 A). These disclosed embodiments reduce the mask cost of fabricating IVRs for different specifications and reduce design time by focusing on a single unit IVR.

Abstract: The present disclosure shows a hybrid regulator topology that can be more easily integrated and that can maintain high efficiency across a wide output and input voltage range, even with a small inductor. The hybrid regulator topology can include two types of regulators: a flying switched-inductor regulator and a step-down regulator that divides the input voltage into an M/N fraction of the input voltage. The disclosed embodiments of the hybrid regulator topology can reduce the capacitive loss of the flying switched-inductor regulator by limiting the voltage swing across the switches in the flying switched-inductor regulator. The disclosed embodiments of the hybrid regulator topology can reduce the inductor resistive loss of the flying switched-inductor regulator by operating the flying switched-inductor regulator at a high switching frequency and with a small amount of current flow through the inductor.

Abstract: The present disclosure shows a hybrid regulator topology that can be more easily integrated and that can maintain high efficiency across a wide output and input voltage range, even with a small inductor. The hybrid regulator topology can include two types of regulators: a flying switched-inductor regulator and a step-down regulator that divides the input voltage into an M/N fraction of the input voltage. The disclosed embodiments of the hybrid regulator topology can reduce the capacitive loss of the flying switched-inductor regulator by limiting the voltage swing across the switches in the flying switched-inductor regulator. The disclosed embodiments of the hybrid regulator topology can reduce the inductor resistive loss of the flying switched-inductor regulator by operating the flying switched-inductor regulator at a high switching frequency and with a small amount of current flow through the inductor.

Abstract: A digital voltage regulator including a dual rail delay chain having large size, feed forward cross-coupled inverters that interconnect the two rails. Stages of the delay chain include a dual-ended output that provides a data signal and a substantially simultaneous data complement signal to a flip-flop component associated with a sampling circuit. In use, the enhanced resolution delay chain and the reduced metastability window flop-flop increase the precision of the digital voltage regulator.

Abstract: A delay chain initialization circuit that converts a singled-sided signal to a dual sided-signal. The dual-sided delay chain including a data rail and a complement rail. Each of the data rail and data complement rail include inverter chains that are interconnected through cross-coupled inverter pairs. The delay chain initialization circuit being adapted to produce, at an output, a data signal and a data complement signal that are substantially simultaneous.

Abstract: A dual rail delay chain having cross-coupled inverters that interconnect the two rails. Delay chain embodiments include cross-coupled inverters that are part of a feed forward signal path between the two rails and are of a larger size than inverters associated with the two rails. The large size feed forward cross-coupled inverters contribute to an enhanced resolution of the delay chain.

Abstract: A sampling circuit including a number of state elements or flip-flops. The state elements or flip-flops are each clocked by a signal that causes them to sample their inputs at a predetermined time. In sampling a plurality of digital inputs, a captured delay chain value is stored by the sampling circuit. Each flip-flop holds one bit and together the total number of bits represent this captured delay chain value. Each flip-flop is provided with a data and a data complement signal as an input, the data and data complement signal being substantially simultaneous. In operation each flip-flop includes a direct connection of the data and data complement signals to a pair of transistors that further operate to capture the logical value carried by the input.

Abstract: A delay chain initialization circuit that converts a singled-sided signal to a dual sided-signal. The dual-sided delay chain including a data rail and a complement rail. Each of the data rail and data complement rail include inverter chains that are interconnected through cross-coupled inverter pairs. The delay chain initialization circuit being adapted to produce, at an output, a data signal and a data complement signal that are substantially simultaneous.