Abstract: A capacitance multiplier includes a self-biasing active load for generating a stable bias voltage without a separate current bias. In addition, the capacitance multiplier includes a cascode load within a multiplying section for increasing the output resistance and in turn the charging/discharging efficiency. Furthermore, the capacitance multiplier is implemented with a plurality of multiplying paths to reduce effects of noise for more stable generation of the multiplied capacitance.

Abstract: A frequency synthesizer is provided. The frequency synthesizer includes an adaptive frequency calibration circuit and a phase locked loop (PLL). The frequency synthesizer performs in a frequency lock mode and in a phase lock mode. In the frequency lock mode, the adaptive frequency calibration circuit compares the frequency of an input signal with the frequency of an output signal of a voltage controlled oscillator of the PLL and outputs control bits as a result of the comparison. The voltage controlled oscillator has a plurality of operating characteristic curves and selects a curve from among the plurality of operating characteristic curves in response to the control bits. In the phase lock mode, the PLL controls an output phase of the voltage controlled oscillator based on a tuning voltage from the selected operating characteristic curve.

Abstract: A capacitance multiplier includes a self-biasing active load for generating a stable bias voltage without a separate current bias. In addition, the capacitance multiplier includes a cascode load within a multiplying section for increasing the output resistance and in turn the charging/discharging efficiency. Furthermore, the capacitance multiplier is implemented with a plurality of multiplying paths to reduce effects of noise for more stable generation of the multiplied capacitance.

Abstract: A capacitance multiplier includes a self-biasing active load for generating a stable bias voltage without a separate current bias. In addition, the capacitance multiplier includes a cascode load within a multiplying section for increasing the output resistance and in turn the charging/discharging efficiency. Furthermore, the capacitance multiplier is implemented with a plurality of multiplying paths to reduce effects of noise for more stable generation of the multiplied capacitance.

Abstract: A capacitance multiplier includes a self-biasing active load for generating a stable bias voltage without a separate current bias. In addition, the capacitance multiplier includes a cascode load within a multiplying section for increasing the output resistance and in turn the charging/discharging efficiency. Furthermore, the capacitance multiplier is implemented with a plurality of multiplying paths to reduce effects of noise for more stable generation of the multiplied capacitance.

Abstract: A local oscillation signal generator and a multi-band transceiver including the local oscillation signal generator are provided. The multi-band transceiver includes a fractional-N phased locked loop (PLL), a local oscillation signal generator, and a transmitter. The fractional-N PLL receives a reference signal and outputs an oscillation signal that is phase-locked to the reference signal. The local oscillation signal generator receives the oscillation signal and outputs a first divided signal that is obtained by dividing a frequency of the oscillation signal by a first value and a second divided signal that is obtained by dividing the frequency of the oscillation signal by a second value. The transmitter receives input signals and generates a transmitter signal using an equation f TX = ( 2 3 ? k - 1 M ) ? f VCO , based on the first divided signal and the second divided signal.

Abstract: A frequency synthesizer is provided. The frequency synthesizer includes an adaptive frequency calibration circuit and a phase locked loop (PLL). The frequency synthesizer performs in a frequency lock mode and in a phase lock mode. In the frequency lock mode, the adaptive frequency calibration circuit compares the frequency of an input signal with the frequency of an output signal of a voltage controlled oscillator of the PLL and outputs control bits as a result of the comparison. The voltage controlled oscillator has a plurality of operating characteristic curves and selects a curve from among the plurality of operating characteristic curves in response to the control bits. In the phase lock mode, the PLL controls an output phase of the voltage controlled oscillator based on a tuning voltage from the selected operating characteristic curve.

Abstract: A phase-locked loop circuit includes a phase detector for comparing the phase of a reference clock signal with the phase of a feedback clock signal and detecting a phase difference between the two; a loop filter in signal communication with the phase detector; a fast frequency lock control circuit in signal communication with the phase detector for disconnecting the phase detector from the loop filter at the initial stage of power on of the phase-locked loop circuit, at least one of supplying constant current to the loop filter for a predetermined time duration and emitting constant current from the loop filter, and then connecting the phase detector to the loop filter; a voltage controlled oscillator in signal communication with the loop filter for generating an output clock signal and varying the frequency of the output clock signal in response to output voltage of the loop filter; and a divider in signal communication with the voltage controlled oscillator for dividing the output clock signal at a predeter

Abstract: A phase-locked loop circuit includes a phase detector for comparing the phase of a reference clock signal with the phase of a feedback clock signal and detecting a phase difference between the two; a loop filter in signal communication with the phase detector; a fast frequency lock control circuit in signal communication with the phase detector for disconnecting the phase detector from the loop filter at the initial stage of power on of the phase-locked loop circuit, at least one of supplying constant current to the loop filter for a predetermined time duration and emitting constant current from the loop filter, and then connecting the phase detector to the loop filter; a voltage controlled oscillator in signal communication with the loop filter for generating an output clock signal and varying the frequency of the output clock signal in response to output voltage of the loop filter; and a divider in signal communication with the voltage controlled oscillator for dividing the output clock signal at a predeter