Abstract: An integrated circuit includes a global power supply node. A first power domain has a first power management circuit, which includes a local power supply node. A first power control circuit is capable of receiving an input signal. A second power control circuit has a higher current capacity than the first power control circuit. The first power control circuit and the second power control circuit are coupled to the local power supply node and the global power supply node. The input signal is configured to initiate a power sequence, e.g., a power up process or a power down process, in the first power control circuit. A first control signal generated by the first power control circuit is configured to initiate a power sequence in the second power control circuit.

Abstract: The memory building blocks can be used in conjunction with ASIC automatic design tools to generate a memory macro (e.g., a memory array) using a known ASIC design flow including, for example, register transfer level (RTL), synthesis, automatic place and route (APR) and timing analysis.

Abstract: A memory including a capacitor coupled to a write bit line or a word line and an initializer configured to initialize a voltage level at a first node between the capacitor and the write bit line or the word line. The memory further includes a controllable initial level adjuster configured to adjust a voltage level of a second node at one terminal of the capacitor in response to a pulse. The capacitor is configured to receive a boost signal at a third node at a terminal opposite the first node. The boost signal configured to change a voltage level of the write bit line or the word line in response to the boost signal.

Abstract: A memory includes a capacitor coupled to a write bit line or a word line. An initializer is configured to initialize a voltage level at a first node between the capacitor and the write bit line or a word line. An initial level adjuster is configured to adjust a voltage level of a second node at one terminal of the capacitor. A pulse generator configured to supply a pulse to the initial level adjuster to control the initial level adjuster. A boost signal is configured to be supplied to a third node on the other terminal of the capacitor opposite the first node to boost a voltage level of the write bit line lower than ground or to boost a voltage level of the word line higher than a power supply voltage.

Abstract: An integrated circuit includes a global power supply node. A first power domain has a first power management circuit, which includes a local power supply node. A first power control circuit is capable of receiving an input signal. A second power control circuit has a higher current capacity than the first power control circuit. The first power control circuit and the second power control circuit are coupled to the local power supply node and the global power supply node. The input signal is configured to initiate a power sequence, e.g., a power up process or a power down process, in the first power control circuit. A first control signal generated by the first power control circuit is configured to initiate a power sequence in the second power control circuit.

Abstract: The memory building blocks can be used in conjunction with ASIC automatic design tools to generate a memory macro (e.g., a memory array) using a known ASIC design flow including, for example, register transfer level (RTL), synthesis, automatic place and route (APR) and timing analysis.

Abstract: An integrated circuit includes a global power supply node. A first power domain has a first power management circuit, which includes a local power supply node. A first power control circuit is capable of receiving an input signal. A second power control circuit has a higher current capacity than the first power control circuit. The first power control circuit and the second power control circuit are coupled to the local power supply node and the global power supply node. The input signal is configured to initiate a power sequence, e.g., a power up process or a power down process, in the first power control circuit. A first control signal generated by the first power control circuit is configured to initiate a power sequence in the second power control circuit.

Abstract: The memory building blocks can be used in conjunction with ASIC automatic design tools to generate a memory macro (e.g., a memory array) using a known ASIC design flow including, for example, register transfer level (RTL), synthesis, automatic place and route (APR) and timing analysis.

Abstract: A memory includes a capacitor coupled to a write bit line or a word line. An initializer is configured to initialize a voltage level at a first node between the capacitor and the write bit line or a word line. An initial level adjuster is configured to adjust a voltage level of a second node at one terminal of the capacitor. A pulse generator configured to supply a pulse to the initial level adjuster to control the initial level adjuster. A boost signal is configured to be supplied to a third node on the other terminal of the capacitor opposite the first node to boost a voltage level of the write bit line lower than ground or to boost a voltage level of the word line higher than a power supply voltage.

Abstract: An integrated circuit includes a global power supply node. A first power domain has a first power management circuit, which includes a local power supply node. A first power control circuit is capable of receiving an input signal. A second power control circuit has a higher current capacity than the first power control circuit. The first power control circuit and the second power control circuit are coupled to the local power supply node and the global power supply node. The input signal is configured to initiate a power sequence, e.g., a power up process or a power down process, in the first power control circuit. A first control signal generated by the first power control circuit is configured to initiate a power sequence in the second power control circuit.

Abstract: The memory building blocks can be used in conjunction with ASIC automatic design tools to generate a memory macro (e.g., a memory array) using a known ASIC design flow including, for example, register transfer level (RTL), synthesis, automatic place and route (APR) and timing analysis.

Abstract: A method and apparatus are provided for sensing in low voltage DRAM memory cells. A method according to one embodiment includes: providing a DRAM circuit having a memory cell, a sense amplifier including a pre-charge circuit connected to a first voltage source and a back-to-back inverter including a first and second NMOS transistor, each having a source and a first and second PMOS transistor, each having a source. The method further includes the steps of maintaining the voltage of the sources of the first and second NMOS transistors at a first voltage during normal operation and lowering the voltage of the sources of the first and second NMOS transistors from the first voltage to a second voltage during a read operation.

Abstract: The disclosure generally relates to a method and apparatus for decreasing the frequency of refreshing a memory cell in communication with a word line and a bit line. A method according to one embodiment includes: providing a DRAM circuit having a memory cell, a sense amplifier including a pre-charge circuit connected to a first voltage source and a back-to-back inverter including a first NMOS transistor having a source, a second NMOS transistor having a source, a first PMOS transistor having a source and a second PMOS transistor having a source; maintaining the voltage of the sources of the first and second PMOS transistors at a first voltage during normal operation; and raising the voltage of the sources of the first and second PMOS transistors from the first voltage to a second voltage during a refresh operation.

Abstract: The disclosure generally relates to a method and apparatus for reading and writing information to a memory cell in communication with a word line and one of a bit line or a complementary bit line. A method according to one embodiment includes: equalizing the bit line and the complementary bit line to a common voltage; addressing the memory cell by connecting the memory cell to one of the bit line or the complementary bit line; reading the memory cell by detecting a first charge stored in the memory cell and communicated said first charge to one of the bit line or the complementary bit line; and writing a second charge into the memory cell by communicating the second charge to the memory cell through an inverter and one of the bit line or the complementary bit line. In one embodiment, the inverter is activated only to communicate the second charge to the memory cell.

Abstract: The disclosure generally relates to a method and apparatus for decreasing the frequency of refreshing a memory cell in communication with a word line and a bit line. A method according to one embodiment includes: providing a DRAM circuit having a memory cell, a sense amplifier including a pre-charge circuit connected to a first voltage source and a back-to-back inverter including a first NMOS transistor having a source, a second NMOS transistor having a source, a first PMOS transistor having a source and a second PMOS transistor having a source; maintaining the voltage of the sources of the first and second PMOS transistors at a first voltage during normal operation; and raising the voltage of the sources of the first and second PMOS transistors from the first voltage to a second voltage during a refresh operation.

Abstract: A method and apparatus are provided for sensing in low voltage DRAM memory cells. A method according to one embodiment includes: providing a DRAM circuit having a memory cell, a sense amplifier including a pre-charge circuit connected to a first voltage source and a back-to-back inverter including a first and second NMOS transistor, each having a source and a first and second PMOS transistor, each having a source. The method further includes the steps of maintaining the voltage of the sources of the first and second NMOS transistors at a first voltage during normal operation and lowering the voltage of the sources of the first and second NMOS transistors from the first voltage to a second voltage during a read operation.

Abstract: The disclosure generally relates to a method and apparatus for reading and writing information to a memory cell in communication with a word line and one of a bit line or a complementary bit line. A method according to one embodiment includes: equalizing the bit line and the complementary bit line to a common voltage; addressing the memory cell by connecting the memory cell to one of the bit line or the complementary bit line; reading the memory cell by detecting a first charge stored in the memory cell and communicated said first charge to one of the bit line or the complementary bit line; and writing a second charge into the memory cell by communicating the second charge to the memory cell through an inverter and one of the bit line or the complementary bit line. In one embodiment, the inverter is activated only to communicate the second charge to the memory cell.