Abstract: An automatic lightness correction method applied to a display panel is disclosed. The automatic display screen lightness compensation method includes steps of: (a) dividing a display area of the display panel into sub-areas; (b) obtaining gamma curve corresponding to each sub-area; (c) selecting a target gamma curve from the gamma curves; (d) adjusting the gamma curves corresponding to the sub-areas to approach the target gamma curve; and (e) using the target gamma curve as a gamma mapping table for the entire display area of the display panel.

Abstract: A power saving method applied to source drivers of a display is disclosed. The method includes steps of: grouping the output channels of each source driver respectively; setting a charge-sharing average register; selecting whether the data signal is reverse processed; calculating an average of the data lines after charge-sharing; calculating the total power consumption of the data signal from the (N?1)-th data line to the N-th data line under all charge-sharing modes, wherein N is a positive integer greater than 1; selecting a candidate lowest power consumption charge-sharing mode corresponding to each source driver; voting the lowest power charge-sharing mode from those candidate lowest power consumption charge-sharing modes; and controlling the operation of each source driver according to the lowest power charge-sharing mode.

Abstract: A circuit layout structure is provided. In the circuit layout structure, a transmission line group is disposed on a substrate. In its first differential signal transmission line pair, a first negative polarity transmission line is parallel to a first positive polarity transmission line and is configured to transmit a first negative polarity transmission signal of a first differential signal. In a second differential signal transmission line pair, a second positive polarity transmission line is parallel to a single-ended signal transmission line and is configured to transmit a second positive polarity transmission signal of a second differential signal. The second negative polarity transmission line is parallel to the second positive polarity transmission line. The single-ended signal transmission line is disposed between the first differential signal transmission line pair and the second differential signal transmission line pair.

Abstract: A signal transmission assembly includes a substrate, a first transmission line, and a second transmission line. The first transmission line and the second transmission line are disposed on the substrate and extending along a first direction. The first transmission line comprises at least one first transmission section and at least one second transmission section. The first transmission section is apart from the second transmission line by a first distance. The second transmission section is apart from the second transmission line by a second distance. The first distance is greater than or equal to the second distance. A first edge of the first transmission section and a second edge of the second transmission section are proximal to the second transmission line and parallel to the first direction, and the second transmission line does not contact an edge extension line extending from the second edge along the first direction.

Abstract: A signal transmission assembly includes a substrate, a first transmission line, and a second transmission line. The first transmission line and the second transmission line are disposed on the substrate and extending along a first direction. The first transmission line comprises at least one first transmission section and at least one second transmission section. The first transmission section is apart from the second transmission line by a first distance. The second transmission section is apart from the second transmission line by a second distance. The first distance is greater than or equal to the second distance. A first edge of the first transmission section and a second edge of the second transmission section are proximal to the second transmission line and parallel to the first direction, and the second transmission line does not contact an edge extension line extending from the second edge along the first direction.

Abstract: The present disclosure provides systems and methods for predicting the future locations of objects that are perceived by autonomous vehicles. An autonomous vehicle can include a prediction system that, for each object perceived by the autonomous vehicle, generates one or more potential goals, selects one or more of the potential goals, and develops one or more trajectories by which the object can achieve the one or more selected goals. The prediction systems and methods described herein can include or leverage one or more machine-learned models that assist in predicting the future locations of the objects. As an example, in some implementations, the prediction system can include a machine-learned static object classifier, a machine-learned goal scoring model, a machine-learned trajectory development model, a machine-learned ballistic quality classifier, and/or other machine-learned models. The use of machine-learned models can improve the speed, quality, and/or accuracy of the generated predictions.

Abstract: An electronic assembly and a method for manufacturing the electronic assembly are provided. The method includes: configuring a chip and a connector at a first wiring layer of a PCB, and determining a first trace between a first pin of the chip and a first pin of the connector, and a second trace between a second pin of the chip and a second pin of the connector according to a first internal resistance of the chip, a second internal resistance of the chip, a first internal resistance of the connector, and a second internal resistance of the connector.

Abstract: A circuit layout structure is provided. In the circuit layout structure, a transmission line group is disposed on a substrate. In its first differential signal transmission line pair, a first negative polarity transmission line is parallel to a first positive polarity transmission line and is configured to transmit a first negative polarity transmission signal of a first differential signal. In a second differential signal transmission line pair, a second positive polarity transmission line is parallel to a single-ended signal transmission line and is configured to transmit a second positive polarity transmission signal of a second differential signal. The second negative polarity transmission line is parallel to the second positive polarity transmission line. The single-ended signal transmission line is disposed between the first differential signal transmission line pair and the second differential signal transmission line pair.

Abstract: An electronic assembly and a method for manufacturing the electronic assembly are provided. The method includes: configuring a chip and a connector at a first wiring layer of a PCB, and determining a first trace between a first pin of the chip and a first pin of the connector, and a second trace between a second pin of the chip and a second pin of the connector according to a first internal resistance of the chip, a second internal resistance of the chip, a first internal resistance of the connector, and a second internal resistance of the connector.

Abstract: Provided herein is a voltage level shifter, an apparatus including a voltage level shifter and a method of converting voltages between input and output power domains. In one embodiment, the voltage level shifter includes: (1) an input circuit configured to receive a data signal from an input power domain and a power down signal from a output power domain and (2) a transition circuit coupled to the input circuit and configured to receive the data signal and an inverted signal of the power down signal, wherein the input circuit and the transition circuit are both configured to connect to a supply voltage of the output power domain as a power source.

Abstract: Provided herein is a voltage level shifter, an apparatus including a voltage level shifter and a method of converting voltages between input and output power domains. In one embodiment, the voltage level shifter includes: (1) an input circuit configured to receive a data signal from an input power domain and a power down signal from a output power domain and (2) a transition circuit coupled to the input circuit and configured to receive the data signal and an inverted signal of the power down signal, wherein the input circuit and the transition circuit are both configured to connect to a supply voltage of the output power domain as a power source.

Abstract: Apparatuses and methods are provided for a self-timed dynamic sense amplifier flop circuit, wherein a pulse generating circuit may be adapted to generate at least a first logic signal based, at least in part, on a first evaluation node signal, and a discharge path circuit comprising at least a first transistor within a first stack of transistors may be operatively responsive to the first timing signal.

Abstract: One embodiment of the present invention sets forth a twelve transistor static random access memory storage cell that provides two write ports and three read ports. The write word line operates at twice the clock frequency. The write bit lines are differential to provide high-performance writes. Each read word line operates at the clock frequency. Single-ended read bit lines are used to provide read performance comparable to write performance. The resulting storage cell only requires four horizontal word lines and five vertical bit lines, enabling very dense, yet high-performance designs.

Abstract: One embodiment of the present invention sets forth a high-speed single-ended memory read circuit that overcomes performance limitations of conventional single ended memory read circuits. A bit line keeper control mechanism for the high-speed single-ended memory read circuit is disclosed that automatically configures the bit line keeper for high-speed operation or low-speed operation, based on the frequency of a system clock. In high-speed operation, the bit line keeper is disabled, thereby eliminating short-circuit currents related to the bit line keeper and increasing the read performance of the single-ended memory read circuit. In low-speed operation, the bit line keeper is periodically disabled by a timer circuit to enable efficient read or write operations. Subsequent to the read or write operation, the bit line keeper is enabled to preserve state on the bit lines. By selectively enabling the bit line keeper, high-speed performance is improved while preserving correct function at low speeds.

Abstract: Embodiments related to fast flip-flops are disclosed.

Abstract: A tire pressure monitoring device, which is disposed in a pneumatic tire and is mounted on a rim of a vehicle, includes a casing, a sensor circuit, a set of electrical contacts, and a cover. The casing defines a battery compartment that receives a battery, and is formed with an opening to permit access in the battery compartment. The sensor circuit is mounted in the casing, and is operable so as to detect a pressure of the pneumatic tire, and so as to generate a signal that corresponds to the detected pressure of the pneumatic tire. The electrical contacts are mounted in the battery compartment of the casing, and are coupled to the sensor circuit and the battery. The cover is connected detachably to the casing so as to cover and uncover selectively the opening of the casing.