Abstract: Received is a main program representing one Engineering Design Optimization Problem (EDOP), the EDOP including polynomial terms with product values. A number (N) of available parallel processors for parallel processing are identified. The main program is partitioned into N subprograms, N being a positive integer greater than one. The N subprograms have fewer overlapping product values between them compared to existing solutions, and the partitioning is prime-number based. Each of the available parallel processors then independently solve a unique subprogram of the N subprograms, resulting in N unique solutions. A best solution is automatically chosen from among the N unique solutions and the best solution is automatically applied to the EDOP.

Abstract: A system for performing operations using linear integer programming for RSA factorization is provided, including an n/e extractor, a prime factorization calculator, a private key determiner, and a decryptor. The n/e extractor is configured to extract a modulus and a public key exponent from a public key. The prime factorization calculator is configured to: determine a semi-prime number of the modulus according to the modulus; use a tail digit and a head digit set of the semi-prime number of the modulus to perform decomposition and factorization with respect to the semi-prime number into two prime factors. The private key determiner is configured to determine a private key using the public key exponent and the two prime numbers. The decryptor is configured to decrypt an encrypted message using the private key so as to generate a decrypted message.

Abstract: A method includes: receiving N sets of weights of a convolutional layer of a neural network, each set of the weights having a same number of weights and corresponding to one of a sequence of output channels (OCs) of the convolutional layer; and performing a pruning process to prune M sets of the weights among the N sets of the weights such that each of the M sets of the weights has a same number of non-zero weights, M being smaller than or equal to N, M being equal to a number of active OCs to be processed in parallel in a neural network processor.

Abstract: A system for performing operations using linear integer programming for RSA factorization is provided, including an n/e extractor, a prime factorization calculator, a private key determiner, and a decryptor. The n/e extractor is configured to extract a modulus and a public key exponent from a public key. The prime factorization calculator is configured to: determine a semi-prime number of the modulus according to the modulus; use a tail digit and a head digit set of the semi-prime number of the modulus to perform decomposition and factorization with respect to the semi-prime number into two prime factors. The private key determiner is configured to determine a private key using the public key exponent and the two prime numbers. The decryptor is configured to decrypt an encrypted message using the private key so as to generate a decrypted message.

Abstract: Received is a main program representing one Engineering Design Optimization Problem (EDOP), the EDOP including polynomial terms with product values. A number (N) of available parallel processors for parallel processing are identified. The main program is partitioned into N subprograms, N being a positive integer greater than one. The N subprograms have fewer overlapping product values between them compared to existing solutions, and the partitioning is prime-number based. Each of the available parallel processors then independently solve a unique subprogram of the N subprograms, resulting in N unique solutions. A best solution is automatically chosen from among the N unique solutions and the best solution is automatically applied to the EDOP.

Abstract: A method of balancing workloads among processing elements (PEs) in a neural network processor can include receiving first weights and second weights of a neural network. The first and second weights are associated with a first and a second output channel (OC), respectively. A first PE computes a partial sum (PSUM) of an output activation of the first OC based on the non-zero weights in the first weights. A second PE computes a PSUM of an output activation of the second OC based on the non-zero weights in the second weights. A controller can allocate one or more non-zero weights of the first weights to the second PE for computing the PSUM of the output activation of the first OC to balance a workload.

Abstract: A universal color coding system, and method of analyzing objects with multiple attributes using the color coding system. The color coding system includes a color mapper arranged to map a plurality of colors with a plurality of numerical codes, wherein the each of the plurality of numerical codes is a unique integer determined based on a combination of prime numbers; wherein each of the plurality of numerical codes is arranged to represent a unique color in color space wherein each of the prime numbers represents a respective basic color of the color space; and wherein the plurality of numerical codes are integers calculated based on addition and multiplication of a plurality of prime numbers.

Abstract: A universal color coding system, and a system and a method of manipulating colors using such color coding system. The color coding system includes a color mapper arranged to map a plurality of colors with a plurality of numerical codes, wherein the each of the plurality of numerical codes is a unique integer determined based on a combination of prime numbers.

Abstract: A universal color coding system, and a system and a method of manipulating colors using such color coding system. The color coding system includes a color mapper arranged to map a plurality of colors with a plurality of numerical codes, wherein the each of the plurality of numerical codes is a unique integer determined based on a combination of prime numbers.

Abstract: A universal color coding system, and method of analyzing objects with multiple attributes using the color coding system. The color coding system includes a color mapper arranged to map a plurality of colors with a plurality of numerical codes, wherein the each of the plurality of numerical codes is a unique integer determined based on a combination of prime numbers; wherein each of the plurality of numerical codes is arranged to represent a unique color in color space wherein each of the prime numbers represents a respective basic color of the color space; and wherein the plurality of numerical codes are integers calculated based on addition and multiplication of a plurality of prime numbers.

Abstract: A deep learning accelerator (DLA) includes processing elements (PEs) grouped into PE groups to perform convolutional neural network (CNN) computations, by applying multi-dimensional weights on an input activation to produce an output activation. The DLA also includes a dispatcher which dispatches input data in the input activation and non-zero weights in the multi-dimensional weights to the processing elements according to a control mask. The DLA also includes a buffer memory which stores the control mask which specifies positions of zero weights in the multi-dimensional weights. The PE groups generate output data of respective output channels in the output activation, and share a same control mask specifying same positions of the zero weights.

Abstract: An image processing apparatus including first circuitry, second circuitry, third circuitry, and fourth circuitry is provided. The first circuitry determines a frame miss rate according to a current frame rate and a target frame rate of an image signal. The second circuitry decreases the target frame rate to the current frame rate when the frame miss rate is greater than a first threshold. The third circuitry increases the target frame rate to an upper-limit frame rate which is determined according to the frame rendering time or memory bandwidth capability, when the frame miss rate is less than a second threshold which is smaller than the first threshold. The fourth circuitry applies the decreased or increased target frame rate for an image to be displayed.

Abstract: An image processing apparatus including first circuitry, second circuitry, third circuitry, and fourth circuitry is provided. The first circuitry determines a frame miss rate according to a current frame rate and a target frame rate of an image signal. The second circuitry decreases the target frame rate to the current frame rate when the frame miss rate is greater than a first threshold. The third circuitry increases the target frame rate to an upper-limit frame rate which is determined according to the frame rendering time or memory bandwidth capability, when the frame miss rate is less than a second threshold which is smaller than the first threshold. The fourth circuitry applies the decreased or increased target frame rate for an image to be displayed.

Abstract: A power management method for an electronic apparatus is provided. The electronic apparatus includes a plurality of heat sources. The power management method includes the following steps: detecting a temperature of the electronic apparatus; detecting a power of the electronic apparatus; identifying an operating scenario of the electronic apparatus; and referring to the detected temperature, the detected power and the operating scenario to determine whether to allocate a power budget between the heat sources.

Abstract: Methods and apparatus are provided for chip aware thermal policies. The thermal performance mapping information is generated. The process obtains a set of process-dependent power data for each process corner of a semiconductor chip, profiles performance data, and selects an operating thermal policy based on the performance data. The thermal policy, based on the process-dependent power data is a mapping formula, or a combination of a mapping formula and a mapping table. The chip aware thermal control is based on process-dependent power data of process corners. The mapping information of process-dependent power data to a corresponding thermal policy is stored in a memory. A thermal policy is applied based on the stored mapping information and an obtained process corner information. The mapping information is applied every time the thermal policy is needed or at boot-up time.

Abstract: Methods and apparatus are provided for chip aware thermal policies. In one novel aspect, the thermal performance mapping information is generated. In one embodiment, the process obtains a set of process-dependent power data for each process corner of a semiconductor chip, profiles performance data, and selects an operating thermal policy based on the performance data. The thermal policy, based on the process-dependent power data is a mapping formula, or a combination of a mapping formula and a mapping table. In another novel aspect, chip aware thermal control is based on process-dependent power data of process corners. In one embodiment, the mapping information of process-dependent power data to a corresponding thermal policy is stored in a memory. A thermal policy is applied based on the stored mapping information and an obtained process corner information. The mapping information is applied every time the thermal policy is needed or at boot-up time.

Abstract: A power budget allocation method includes: obtaining a system setting associated with a multi-core processor system, obtaining a target power budget, and checking, by a power management controller, at least one power management table according to the system setting and the target power budget to generate a power management output for the multi-core processor system. The system setting includes a core combination setting of the multi-core processor system, and further includes a frequency setting of each processor core selected by the core combination setting.

Abstract: A battery balance circuit is adapted to balance battery voltages among a plurality of battery cells. The battery balance circuit is enabled to perform a battery balance process when the battery cells are charged, and is disabled when one of the batter cells is fully charged or the battery cells are un-charged.

Abstract: A method of cloning data in a memory for a source virtual machine (VM) and at least one cloned virtual machine is proposed. A mapping relationship between a guest physical address from the source VM or the cloned VM and a host physical address of the memory is defined by a plurality of page tables configured in a plurality of hierarchical levels. In the method, metadata of the page tables in the highest level or the higher levels of the plurality of hierarchical levels is copied to the virtual machine. Remaining metadata of the page tables in the levels other than the highest level or the higher levels of the plurality of hierarchical levels is replicated to the virtual machine in response to the access operation. Data stored in the corresponding address of the memory is accessed according to the metadata and the replicated metadata.

Abstract: A method and a computer system for memory management on a virtual machine system are provided. The memory management method includes the following steps. A least recently used (LRU) list is maintained by at least one processor according to a last access time, wherein the LRU list includes a plurality of memory pages. A first portion of the memory pages are stored in a virtual memory, a second portion of the memory pages are stored in a zram driver, and a third portion of the memory pages are stored in at least one swap disk. A space in the zram driver is set by the at least one processor. The space in the zram driver is adjusted by the processor according to a plurality of access probabilities of the memory pages in the zram driver, an overhead of a pseudo page fault, and an overhead of a true page fault.