Patents by Inventor Han-Ming Wu

Han-Ming Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150164273
    Abstract: A grill pan includes a flat portion and two slanting portions. The slanting portions are connected to each side of the flat portion respectively. Each of the slanting portions is formed with a spout positioned opposite to where the flat portion and the slanting portion meet. The slanting portions are slightly higher than the flat portion to divide a cooking area for low-fat food and a cooking area for high-fat food, and the slanting portions slope downward from the flat portion to allow any fluid on the cooking area for high-fat food to flow toward the spout instead of the cooking area for low-fat food during cooking.
    Type: Application
    Filed: May 23, 2014
    Publication date: June 18, 2015
    Applicant: TSANN KUEN (ZHANG ZHOU) ENTERPRISE CO., LTD.
    Inventors: NAI-CHIANG PAI, HAN-MING WU, YU-CHENG CHEN
  • Patent number: 7977254
    Abstract: A method of forming a gate insulator in the manufacture of a semiconductor device comprises conducting a photo-assisted electrochemical process to form a gate-insulating layer on a gallium nitride layer of the semiconductor device, wherein the gate-insulating layer includes gallium oxynitride and gallium oxide, and performing a rapid thermal annealing process. The photo-assisted electrochemical process uses an electrolyte bath including buffered CH3COOH at a pH between about 5.5 and 7.5. The rapid thermal annealing process is conducted in O2 environment at a temperature between about 500° C. and 800° C.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: July 12, 2011
    Assignee: Tekcore Co., Ltd.
    Inventors: Lung-Han Peng, Han-Ming Wu, Jing-Yi Lin
  • Publication number: 20110124203
    Abstract: A method of forming a gate insulator in the manufacture of a semiconductor device comprises conducting a photo-assisted electrochemical process to form a gate-insulating layer on a gallium nitride layer of the semiconductor device, wherein the gate-insulating layer includes gallium oxynitride and gallium oxide, and performing a rapid thermal annealing process. The photo-assisted electrochemical process uses an electrolyte bath including buffered CH3COOH at a pH between about 5.5 and 7.5. The rapid thermal annealing process is conducted in O2 environment at a temperature between about 500° C. and 800° C.
    Type: Application
    Filed: June 27, 2007
    Publication date: May 26, 2011
    Inventors: Lung-Han Peng, Han-Ming Wu, Jing-Yi Lin
  • Patent number: 7256872
    Abstract: A method and apparatus are described for removing an initial gas from a gas-filled enclosure between the mask-protective device, such as a pellicle, and the patterned mask, such as a reticle, and adding a purge gas with a different composition. The gas-filled enclosure includes a vent for adding the purge gas to the chamber and removing the initial gas from the chamber. Adding and removing may be accomplished by using pressure, diffusion, vacuum, or other means.
    Type: Grant
    Filed: January 16, 2004
    Date of Patent: August 14, 2007
    Assignee: Intel Corporation
    Inventors: Han-Ming Wu, Ronald J. Kuse
  • Patent number: 7253061
    Abstract: A method of forming a gate insulator in the manufacture of a semiconductor device comprises conducting a photo-assisted electrochemical process to form a gate-insulating layer on a gallium nitride layer of the semiconductor device, wherein the gate-insulating layer includes gallium oxynitride and gallium oxide, and performing a rapid thermal annealing process. The photo-assisted electrochemical process uses an electrolyte bath including buffered CH3COOH at a pH between about 5.5 and 7.5. The rapid thermal annealing process is conducted in O2 environment at a temperature between about 500° C. and 800° C.
    Type: Grant
    Filed: December 6, 2004
    Date of Patent: August 7, 2007
    Assignee: Tekcore Co., Ltd.
    Inventors: Lung-Han Peng, Han-Ming Wu, Jing-Yi Lin
  • Patent number: 7223448
    Abstract: A method for providing uniformity in plasma-assisted material processes. A shielding plate is implemented within a plasma chamber above a substrate. The dimensions, geometry, and location of the shielding plate are optimized to generate a desired ion flux in a plasma-assisted material process conducted in a plasma chamber.
    Type: Grant
    Filed: March 24, 2003
    Date of Patent: May 29, 2007
    Assignee: Intel Corporation
    Inventors: Han-Ming Wu, He Long
  • Publication number: 20060121700
    Abstract: A method of forming a gate insulator in the manufacture of a semiconductor device comprises conducting a photo-assisted electrochemical process to form a gate-insulating layer on a gallium nitride layer of the semiconductor device, wherein the gate-insulating layer includes gallium oxynitride and gallium oxide, and performing a rapid thermal annealing process. The photo-assisted electrochemical process uses an electrolyte bath including buffered CH3COOH at a pH between about 5.5 and 7.5. The rapid thermal annealing process is conducted in O2 environment at a temperature between about 500° C. and 800° C.
    Type: Application
    Filed: December 6, 2004
    Publication date: June 8, 2006
    Inventors: Lung-Han Peng, Han-Ming Wu, Jing-Yi Lin
  • Patent number: 7022597
    Abstract: A method for manufacturing gallium nitride based transparent conductive oxidized film ohmic electrodes includes forming a transparent conductive film on a GaN layer, forming a transparent conductive hetero-junction of opposing electrical characteristics on a transparent conductive film on the surface of the GaN layer through an ion diffusion process, and laying a metallic thick film on the surface of the transparent conductive hetero-junction for wiring process in the later fabrication operation. Thus through the electron and hole tunneling effect in the ion diffusion process the Fermi level of the hetero-junction may be improved to form an ohmic contact electrode.
    Type: Grant
    Filed: July 16, 2004
    Date of Patent: April 4, 2006
    Assignee: Tekcore Co., Ltd.
    Inventors: Lung-Han Peng, Han-Ming Wu, Sung-Li Wang, Chia-Wei Chang, Chin-Yi Lin
  • Publication number: 20060014368
    Abstract: A method for manufacturing gallium nitride based transparent conductive oxidized film ohmic electrodes includes forming a transparent conductive film on a GaN layer, forming a transparent conductive hetero-junction of opposing electrical characteristics on a transparent conductive film on the surface of the GaN layer through an ion diffusion process, and laying a metallic thick film on the surface of the transparent conductive hetero-junction for wiring process in the later fabrication operation. Thus through the electron and hole tunneling effect in the ion diffusion process the Fermi level of the hetero-junction may be improved to form an ohmic contact electrode.
    Type: Application
    Filed: July 16, 2004
    Publication date: January 19, 2006
    Inventors: Lung-Han Peng, Han-Ming Wu, Sung-Li Wang, Chia-Wei Chang, Chin-Yi Lin
  • Publication number: 20050139317
    Abstract: An apparatus comprising a plasma chamber containing a plasma for a plasma-assisted material process upon a substrate; a shielding plate within the plasma chamber to actively direct ion flux to desired areas of the substrate; and a supporting structure to support the shielding plate within the chamber is disclosed.
    Type: Application
    Filed: November 3, 2004
    Publication date: June 30, 2005
    Inventors: Han-Ming Wu, He Long
  • Patent number: 6793717
    Abstract: The present invention includes a filtered mask enclosure having an exterior portion and interior regions within the exterior portion such that the interior regions have a filtering region and a purging region connected to the filtering region. The present invention further includes a method of removing a first contaminant in a gas phase, a second contaminant in a solid phase, and a third contaminant having an electrical charge from a purge gas and flowing the purge gas through a vicinity of a mask while exposing a wafer with light through the mask.
    Type: Grant
    Filed: June 11, 2003
    Date of Patent: September 21, 2004
    Assignee: Intel Corporation
    Inventors: Han-Ming Wu, Giang Dao
  • Publication number: 20040145716
    Abstract: A method and apparatus are described for removing an initial gas from a gas-filled enclosure between the mask-protective device, such as a pellicle, and the patterned mask, such as a reticle, and adding a purge gas with a different composition. The gas-filled enclosure includes a vent for adding the purge gas to the chamber and removing the initial gas from the chamber. Adding and removing may be accomplished by using pressure, diffusion, vacuum, or other means.
    Type: Application
    Filed: January 16, 2004
    Publication date: July 29, 2004
    Inventors: Han-Ming Wu, Ronald J. Kuse
  • Publication number: 20040099376
    Abstract: Plasma etching is controlled utilizing two etchant gases to form a plasma so as to obtain controlled (e.g., uniform) etch rate across a wafer. One etchant gas forms appositive plasma, which is the dominant plasma. The other etchant gas forms a negative plasma, which is the secondary plasma. The ratio of dominant plasma to the secondary plasma can be adjusted such that ion densities are uniform across the wafer, resulting in uniform etch rate over the wafer.
    Type: Application
    Filed: November 21, 2003
    Publication date: May 27, 2004
    Applicant: Intel Corporation, a Delaware corporation
    Inventors: Y. Long He, Albert Kwok, Tsukasa Abe, Han-Ming Wu
  • Patent number: 6737358
    Abstract: Plasma etching is controlled utilizing two etchant gases to form a plasma so as to obtain controlled (e.g., uniform) etch rate across a wafer. One etchant gas forms a positive plasma, which is the dominant plasma. The other etchant gas forms a negative plasma, which is the secondary plasma. The ratio of dominant plasma to the secondary plasma can be adjusted such that ion densities are uniform across the wafer, resulting in uniform etch rate over the wafer.
    Type: Grant
    Filed: February 13, 2002
    Date of Patent: May 18, 2004
    Assignee: Intel Corporation
    Inventors: Y. Long He, Albert Kwok, Tsukasa Abe, Han-Ming Wu
  • Patent number: 6710845
    Abstract: A method and apparatus are described for removing an initial gas from a gas-filled enclosure between the mask-protective device, such as a pellicle, and the patterned mask, such as a reticle, and adding a purge gas with a different composition. The gas-filled enclosure includes a vent for adding the purge gas to the enclosure and removing the initial gas from the enclosure. Adding and removing may be accomplished by using pressure, diffusion, or vacuum.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: March 23, 2004
    Assignee: Intel Corporation
    Inventors: Han-Ming Wu, Ronald J. Kuse
  • Publication number: 20040045433
    Abstract: The present invention includes a filtered mask enclosure having an exterior portion and interior regions within the exterior portion such that the interior regions have a filtering region and a purging region connected to the filtering region. The present invention further includes a method of removing a first contaminant in a gas phase, a second contaminant in a solid phase, and a third contaminant having an electrical charge from a purge gas and flowing the purge gas through a vicinity of a mask while exposing a wafer with light through the mask.
    Type: Application
    Filed: June 11, 2003
    Publication date: March 11, 2004
    Inventors: Han-Ming Wu, Giang Dao
  • Publication number: 20030226503
    Abstract: An apparatus comprising a plasma chamber containing a plasma for a plasma-assisted material process upon a substrate; a shielding plate within the plasma chamber to actively direct ion flux to desired areas of the substrate; and a supporting structure to support the shielding plate within the chamber is disclosed.
    Type: Application
    Filed: March 24, 2003
    Publication date: December 11, 2003
    Inventors: Han-Ming Wu, He Long
  • Patent number: 6610123
    Abstract: The present invention includes a filtered mask enclosure having an exterior portion and interior regions within the exterior portion such that the interior regions have a filtering region and a purging region connected to the filtering region. The present invention further includes a method of removing a first contaminant in a gas phase, a second contaminant in a solid phase, and a third contaminant having an electrical charge from a purge gas and flowing the purge gas through a vicinity of a mask while exposing a wafer with light through the mask.
    Type: Grant
    Filed: December 17, 2001
    Date of Patent: August 26, 2003
    Assignee: Intel Corporation
    Inventors: Han-Ming Wu, Giang Dao
  • Patent number: D730679
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: June 2, 2015
    Assignee: TSANN KUEN (ZHANGZHOU) ENTERPRISE CO., LTD.
    Inventor: Han-Ming Wu
  • Patent number: D755010
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: May 3, 2016
    Assignee: Tsann Kuen (Zhangzhou) Enterprise Co., Ltd.
    Inventor: Han-Ming Wu