Patents by Inventor Hann-Huei Tsai

Hann-Huei Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10914805
    Abstract: A signal error calibrating method is disclosed herein and includes following steps: filtering an error voltage in a sensor by a low pass filter in a calibration mode; converting the offset voltage to be a digital offset signal by an analog digital signal converter; converting the digital offset signal to be an offset calibrating signal by a digital analog signal converter; transmitting the offset calibrating signal to an input end of the sensor so as to offset an error voltage at the input end of the sensor. After calibrating the error voltage, the analog digital converter in the error calibrating circuit can be used for the need of signal output and the low pass filter is turned off at the same time.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: February 9, 2021
    Assignee: National Applied Research Laboratories
    Inventors: Chih-Yuan Yeh, Po-Chang Wu, Hann-Huei Tsai, Ying-Zong Juang
  • Patent number: 10656184
    Abstract: A signal process circuit includes a signal modulation unit, a first resistor, a second resistor, a first discharge unit, a second discharge unit and a discharge detection unit. The signal modulation unit is used to modulate an input signal for generating a modulated signal. The first resistor is coupled between the signal modulation unit and an operation node. The second resistor is coupled between the operation node and the signal modulation unit. The first discharge unit is coupled to the signal modulation unit. The discharge unit is coupled to the signal modulation unit. The discharge detection unit is coupled to the first discharge unit, the operation node and the second discharge unit for detecting an output common voltage and control a discharge path accordingly.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: May 19, 2020
    Assignee: NATIONAL APPLIED RESEARCH LABORATORIES
    Inventors: Ying-Zong Juang, Hann-Huei Tsai, Po-Chang Wu, Yu-Chen Liu, Chih-Yuan Yeh
  • Publication number: 20190271753
    Abstract: A signal error calibrating method is disclosed herein and includes following steps: filtering an error voltage in a sensor by a low pass filter in a calibration mode; converting the offset voltage to be a digital offset signal by an analog digital signal converter; converting the digital offset signal to be an offset calibrating signal by a digital analog signal converter; transmitting the offset calibrating signal to an input end of the sensor so as to offset an error voltage at the input end of the sensor. After calibrating the error voltage, the analog digital converter in the error calibrating circuit can be used for the need of signal output and the low pass filter is turned off at the same time.
    Type: Application
    Filed: April 17, 2018
    Publication date: September 5, 2019
    Inventors: CHIH-YUAN YEH, PO-CHANG WU, HANN-HUEI TSAI, YING-ZONG JUANG
  • Patent number: 9702894
    Abstract: The present invention discloses a monolithic z-axis torsional CMOS MEMS accelerometer, it includes a matching frame, two anchors, a first comb structure, a second comb structure and a proof mass. With the implementation of the present invention, the capacitance sensitivity of Z+ direction and Z? direction sensing signals by the accelerometer can be improved. On the other hand, due to the feasibility of applying micromachining etch processes from the top side, the ease and the yield of production are both promoted.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: July 11, 2017
    Assignee: NATIONAL APPLIED RESEARCH LABORATORIES
    Inventors: Sheng-Hsiang Tseng, Yi-Jen Wang, Hann-Huei Tsai, Ying-Zong Juang
  • Publication number: 20170070193
    Abstract: The invention provides an RF power amplifier with post-distortion linearizer. The power amplifier includes a main amplifier, an auxiliary amplifier and a phase compensator. The first amplifier has a first input end and a first output end and operates in class A or AB. The auxiliary amplifier has a second input end and a second output end and operates in class B or C. The second output end connects the first output end to form a signal output end. The phase compensator has a third input end and a third output end and compensates a phase difference between the main and auxiliary amplifiers to make outputs of the two amplifiers opposite in phase. The third output end connects the second input end. The third input end connects the first input end to form a signal input end.
    Type: Application
    Filed: November 22, 2015
    Publication date: March 9, 2017
    Applicant: NATIONAL APPLIED RESEARCH LABORATORIES
    Inventors: Ying-Zong Juang, Hann-Huei Tsai, Po-Chang Wu, Kuei-Cheng Lin, Chih-Yuan Yeh, Hwann-Kaeo Chiou
  • Patent number: 9548673
    Abstract: The invention includes two parallel paths. A first path is composed of two contact ends of a first electronic switch and a first, third and fifth diodes, which connect in series. One contact end connects a first end of an AC source, and a control end connects a second end of the AC source. A second path is composed of two contact ends of a second electronic switch and a second, fourth and sixth diodes, which connect in series. One contact end connects the second end of the AC source, and a control end connects the first end of the AC source. The AC source is connected between the positive ends of the first and second diodes. The second end of the AC source separately connects negative ends of the first and third diodes through two capacitors. The first end of the AC source separately connects negative ends of the second and fourth diodes through another two capacitors. Negative ends of the fifth and sixth diodes connect together to form a voltage output end.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: January 17, 2017
    Assignee: NATIONAL APPLIED RESEARCH LABORATORIES
    Inventors: Ying-Zong Juang, Hann-Huei Tsai, Po-Chang Wu, Kuei-Cheng Lin, Chih-Yuan Yeh
  • Publication number: 20160187369
    Abstract: The present invention discloses a monolithic z-axis torsional CMOS MEMS accelerometer, it includes a curl matching frame, two anchors, a first comb structure, a second comb structure and a proof mass. With the implementation of the present invention, the capacitance sensitivity of Z+ direction and Z? direction sensing signals by the accelerometer can be improved. On the other hand, due to the feasibility of applying micromachining etch processes from the top side, the ease and the yield of production are both promoted.
    Type: Application
    Filed: February 18, 2015
    Publication date: June 30, 2016
    Inventors: Sheng-Hsiang TSENG, Yi-Jen WANG, Hann-Huei TSAI, Ying-Zong JUANG
  • Patent number: 9118338
    Abstract: A current-steering offset compensation circuit is configured for compensating an offset caused by process variation or environment variation of a signal processor. The signal processor includes a pair of differential input terminals and a pair of differential output terminals. The current-steering offset compensation circuit comprises a current-steering circuit connected with the signal processor, a digital control unit which generates a digital control signal according to the outputs from the pair of differential output terminals of the signal processor, and a digital-to-analog converter which receives the digital control signal and outputs a control voltage, wherein the current-steering circuit receives the control voltage, so as to steer the current of the pair of differential input terminals, to reduce the offset in the signal processor.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: August 25, 2015
    Assignee: NATIONAL APPLIED RESEARCH LABORATORIES
    Inventors: Ying-Zong Juang, Hann-Huei Tsai, Po-Chang Wu, Chih-Yuan Yeh, Kuei-Cheng Lin
  • Publication number: 20150168362
    Abstract: A microfluidic channel detection system for environmental or biomedical detection includes a chip having a first surface where a sensing region is located, a substrate having a recess for containing the chip, in which the first surface is exposed, a first inactive layer filling gaps between the chip and the substrate in the recess, so as to form a plane with the first surface of the chip, an electrical connection member electrically connected to the chip, a cover having a microfluidic channel and disposed on the plane. The flow path in the microfluidic channel is smooth, and further the measurement accuracy is improved via the plane formed by the first inactive layer and the first surface.
    Type: Application
    Filed: February 20, 2014
    Publication date: June 18, 2015
    Applicant: National Applied Research Laboratories
    Inventors: Che-Hsin LIN, Jun-Jie WANG, Ying-Zong JUANG, Hann-Huei TSAI, Hsin-Hao LIAO
  • Publication number: 20150171885
    Abstract: A current-steering offset compensation circuit is configured for compensating an offset caused by process variation or environment variation of a signal processor. The signal processor includes a pair of differential input terminals and a pair of differential output terminals. The current-steering offset compensation circuit comprises a current-steering circuit connected with the signal processor, a digital control unit which generates a digital control signal according to the outputs from the pair of differential output terminals of the signal processor, and a digital-to-analog converter which receives the digital control signal and outputs a control voltage, wherein the current-steering circuit receives the control voltage, so as to steer the current of the pair of differential input terminals, to reduce the offset in the signal processor.
    Type: Application
    Filed: February 7, 2014
    Publication date: June 18, 2015
    Applicant: National Applied Research Laboratories
    Inventors: Ying-Zong JUANG, Hann-Huei Tsai, Po-Chang Wu, Chih-Yuan Yeh, Kuei-Cheng Lin
  • Patent number: 8704278
    Abstract: A structure for a metal-oxide-semiconductor field-effect transistor (MOSFET) sensor is provided. The structure includes a MOSFET, a sensing membrane, and a reference electrode. The reference electrode and the sensing membrane are formed on the first surface of the MOSFET and are arranged in such a way that the reference electrode and the sensing membrane are uniformly and electrically coupled to each other. Thus, the electric field between the sensing membrane and the reference electrode is uniformly distributed therebetween to stabilize the working signal of the MOSFET sensor.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: April 22, 2014
    Assignee: Seoul National University Industry Foundation
    Inventors: Ying-Zong Juang, Hann-Huei Tsai, Hsin-Hao Liao, Chen-Fu Lin
  • Patent number: 8704580
    Abstract: The present invention discloses a circuit sharing time delay integrator structure. The major composing elements of this circuit sharing time delay integrator structure are: a sharing circuit, a first control block, a plurality of second control blocks and a timing set generated by a timing generator circuit. The sharing circuit can be an OP-AMP, an active load, or any of a variety of combinations used in signal accumulation applications. With the implementation of the present invention to applications of signal accumulations, the necessity of an adder circuitry is eliminated, the overall circuitry and hence the total amount of transistors required when producing the integrated circuit is massively reduced, and thus a great cost reduction and better timing and power efficiency can all be thereof achieved.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: April 22, 2014
    Assignee: National Applied Research Laboratories
    Inventors: Chin-Fong Chiu, Hann-Huei Tsai, Wen-Hsu Chang, Chih-Cheng Hsieh, Kuo-Wei Cheng
  • Publication number: 20130335132
    Abstract: The present invention discloses a circuit sharing time delay integrator structure. The major composing elements of this circuit sharing time delay integrator structure are: a sharing circuit, a first control block, a plurality of second control blocks and a timing set generated by a timing generator circuit. The sharing circuit can be an OP-AMP, an active load, or any of a variety of combinations used in signal accumulation applications. With the implementation of the present invention to applications of signal accumulations, the necessity of an adder circuitry is eliminated, the overall circuitry and hence the total amount of transistors required when producing the integrated circuit is massively reduced, and thus a great cost reduction and better timing and power efficiency can all be thereof achieved.
    Type: Application
    Filed: August 24, 2012
    Publication date: December 19, 2013
    Applicant: National Applied Research Laboratories
    Inventors: Chin-Fong CHIU, Hann-Huei TSAI, Wen-Hsu CHANG, Chih-Cheng HSIEH, Kuo-Wei CHENG
  • Publication number: 20130153969
    Abstract: A structure for a metal-oxide-semiconductor field-effect transistor (MOSFET) sensor is provided. The structure includes a MOSFET, a sensing membrane, and a reference electrode. The reference electrode and the sensing membrane are formed on the first surface of the MOSFET and are arranged in such a way that the reference electrode and the sensing membrane are uniformly and electrically coupled to each other. Thus, the electric field between the sensing membrane and the reference electrode is uniformly distributed therebetween to stabilize the working signal of the MOSFET sensor.
    Type: Application
    Filed: March 13, 2012
    Publication date: June 20, 2013
    Applicant: National Chip Implementation Center National Applied Research Laboratories
    Inventors: Ying-Zong JUANG, Hann-Huei Tsai, Hsin-Hao Liao, Chen-Fu Lin
  • Patent number: 8466521
    Abstract: A hydrogen ion-sensitive field effect transistor and a manufacturing method thereof are provided. The hydrogen ion-sensitive field effect transistor includes a semiconductor substrate, an insulating layer, a transistor gate, and a sensing film. A gate area is defined on the semiconductor substrate having a source area and a drain area. The insulating layer is formed within the gate area on the semiconductor substrate. The transistor gate is deposited within the gate area and includes a first gate layer. Further, the first gate layer is an aluminum layer, and a sensing window is defined thereon. The sensing film is an alumina film formed within the sensing window by oxidizing the first gate layer. Thus, the sensing film is formed without any film deposition process, and consequently the manufacturing method is simplified.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: June 18, 2013
    Assignee: National Chip Implementation Center National Applied Research Laboratories
    Inventors: Chin-Long Wey, Chin-Fong Chiu, Ying-Zong Juang, Hann-Huei Tsai, Chen-Fu Lin
  • Publication number: 20130146899
    Abstract: A complementary metal-oxide semiconductor (CMOS) sensor with an image sensing unit integrated therein is provided. The CMOS sensor includes a first substrate, a CMOS circuit, and a sensing device. The first substrate has the image sensing unit formed thereon. The CMOS circuit is disposed on the first substrate and has a receiving space. The sensing device is disposed in the receiving space. The image sensing unit is located at a position from which the image sensing unit can monitor the sensing device. Accordingly, the image sensing unit monitors the sensing device by sensing its image.
    Type: Application
    Filed: February 29, 2012
    Publication date: June 13, 2013
    Applicant: National Chip Implementation Center National Applied Research Laboratories
    Inventors: Ying-Zong JUANG, Hann-Huei Tsai, Hsin-Hao Liao, Chen-Fu Lin
  • Patent number: 8451078
    Abstract: A CMOS-MEMS switch structure is disclosed. The CMOS-MEMS switch structure includes a first substrate, a second substrate, a first cantilever beam, and a second cantilever beam. The first and second substrates are positioned opposite each other. The first cantilever beam is provided on the first substrate, extends from the first substrate toward the second substrate, and bends downward. Likewise, the second cantilever beam is provided on the second substrate, extends from the second substrate toward the first substrate, and bends downward. The first and second substrates are movable toward each other to connect a first top surface of the first cantilever beam and a second top surface of the second cantilever beam, and away from each other so that the first top surface of the first cantilever beam and the second top surface of the second cantilever beam are disconnected, thereby closing or opening the CMOS-MEMS switch structure.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: May 28, 2013
    Assignees: National Chip Implementation Center, National Applied Research Laboratories
    Inventors: You-Liang Lai, Ying-Zong Juang, Hann-Huei Tsai, Sheng-Hsiang Tseng, Chin-Fong Chiu
  • Patent number: 8410480
    Abstract: The present invention discloses a CMOS-MEMS cantilever structure. The CMOS-MEMS cantilever structure includes a substrate, a circuit structure, and a cantilever beam. The substrate has a circuit area and a sensor unit area defined thereon. The circuit structure is formed in the circuit area. The cantilever beam is disposed in the sensor unit area with one end floating above the substrate and the other end connecting to the circuit structure. With the above arrangement, the manufacturing process of CMOS-MEMS cantilever structure of this invention can be simplified. Furthermore, the structure of the cantilever beam is thinned down and therefore has a higher sensitivity.
    Type: Grant
    Filed: February 19, 2010
    Date of Patent: April 2, 2013
    Assignee: National Chip Implementation Center National Applied Research Laboratories
    Inventors: Chin-Fong Chiu, Ying Zong Juang, Hann Huei Tsai, Sheng-Hsiang Tseng, Chen-Fu Lin
  • Publication number: 20120279838
    Abstract: A CMOS-MEMS switch structure is disclosed. The CMOS-MEMS switch structure includes a first substrate, a second substrate, a first cantilever beam, and a second cantilever beam. The first and second substrates are positioned opposite each other. The first cantilever beam is provided on the first substrate, extends from the first substrate toward the second substrate, and bends downward. Likewise, the second cantilever beam is provided on the second substrate, extends from the second substrate toward the first substrate, and bends downward. The first and second substrates are movable toward each other to connect a first top surface of the first cantilever beam and a second top surface of the second cantilever beam, and away from each other so that the first top surface of the first cantilever beam and the second top surface of the second cantilever beam are disconnected, thereby closing or opening the CMOS-MEMS switch structure.
    Type: Application
    Filed: June 15, 2011
    Publication date: November 8, 2012
    Applicant: National Chip Implementation Center National Applied Research Laboratories.
    Inventors: You-Liang LAI, Ying-Zong JUANG, Hann-Huei TSAI, Sheng-Hsiang TSENG, Chin-Fong CHIU
  • Patent number: 8158063
    Abstract: A biosensor package structure with a micro-fluidic channel is provided. The biosensor package structure includes a substrate, a biochip, and a cover. The substrate has a first surface, a second surface, and an opening. The biochip is attached on the first surface. A bio-sensing area of the biochip is exposed to the opening of the substrate. The cover is attached on the second surface to cover the opening so as to form a micro-fluidic channel. By implementing the invention, the manufacturing process of the biosensor is simplified and the productivity is increased.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: April 17, 2012
    Assignee: National Chip Implementation Center National Applied Research Laboratories
    Inventors: Chin-Fong Chiu, Ying-Zong Juang, Hann-Huei Tsai, Chen-Fu Lin