Abstract: The present disclosure provides a semiconductor package including a substrate, a display unit, a flexible substrate, a driving circuit, and a memory. The substrate has a first surface and a second surface opposite to each other, and the first surface has a display region and a bonding region. The display unit is disposed on the display region of the first surface. The flexible substrate is disposed below the second surface and has a connection portion extended to the bonding region of the first surface. The driving circuit is disposed on the flexible substrate and electrically connects with the display unit. The memory is disposed on the flexible substrate and electrically connects with the driving circuit.

Abstract: The present disclosure provides a semiconductor package including a substrate, a display unit, a driving circuit, and at least one of memory. The substrate has a display region and a peripheral region. The display unit is disposed in the display region and electrically connects with the display unit. The memory is disposed in the peripheral region and electrically connected with the driving circuit. The driving circuit and the memory are spaced apart from each other.

Abstract: The present disclosure provides a semiconductor package including a substrate, a display unit, a driving circuit, and at least one of memory. The substrate has a display region and a peripheral region. The display unit is disposed in the display region and electrically connects with the display unit. The memory is disposed in the peripheral region and electrically connected with the driving circuit. The driving circuit and the memory are spaced apart from each other.

Abstract: A flash memory with assistant gates, including two floating gates disposed on a substrate, an insulating layer formed on the two floating gates and the substrate, an assistant gate disposed between the two floating gates, wherein a portion of the assistant gate wraps around the two floating gates, and two select gates disposed respectively outside the two floating gates and partially overlap the two floating gates.

Abstract: A flash memory with assistant gates, including two floating gates disposed on a substrate, an insulating layer formed on the two floating gates and the substrate, an assistant gate disposed between the two floating gates, wherein a portion of the assistant gate wraps around the two floating gates, and two select gates disposed respectively outside the two floating gates and partially overlap the two floating gates.

Abstract: The present disclosure provides a semiconductor package including a substrate, a display unit, a flexible substrate, a driving circuit, and a memory. The substrate has a first surface and a second surface opposite to each other, and the first surface has a display region and a bonding region. The display unit is disposed on the display region of the first surface. The flexible substrate is disposed below the second surface and has a connection portion extended to the bonding region of the first surface. The driving circuit is disposed on the flexible substrate and electrically connects with the display unit. The memory is disposed on the flexible substrate and electrically connects with the driving circuit.

Abstract: The present disclosure provides a semiconductor package including a substrate, a display unit, a flexible circuit board, a driving circuit, and a memory. The substrate has a first surface and a second surface opposite to each other, and the first surface has a display region and a bonding region. The display unit is disposed on the display region of the first surface. The flexible circuit board is disposed below the second surface and has a connection portion extended to the bonding region of the first surface. The driving circuit is disposed on the flexible circuit board and electrically connects to the display unit. The memory is disposed on the flexible circuit board and electrically connects to the driving circuit.

Abstract: A method of manufacturing semiconductor devices having self-aligned contacts is provided. Multiple isolation structures are formed on the substrate to define an active area. Multiple gate structures are formed on the substrate. Multiple doped areas are formed in the substrate beside each gate structure. Multiple first spacers are formed on the sidewalls of each of the gate structure. Multiple second spacers are formed on the sidewalls of each of the isolation structure. A dielectric layer is formed on the substrate. Then, a self-aligned process is performed to form multiple contact openings in the dielectric layer between the gate structures. The conductive material is filled in the contact openings.

Abstract: A method of manufacturing semiconductor devices having self-aligned contacts is provided. Multiple isolation structures are formed on the substrate to define an active area. Multiple gate structures are formed on the substrate. Multiple doped areas are formed in the substrate beside each gate structure. Multiple first spacers are formed on the sidewalls of each of the gate structure. Multiple second spacers are formed on the sidewalls of each of the isolation structure. A dielectric layer is formed on the substrate. Then, a self-aligned process is performed to form multiple contact openings in the dielectric layer between the gate structures. The conductive material is filled in the contact openings.

Abstract: A method of manufacturing semiconductor devices having self-aligned contacts is provided. Multiple isolation structures are formed on the substrate to define an active area. Multiple gate structures are formed on the substrate. Multiple doped areas are formed in the substrate beside each gate structure. Multiple first spacers are formed on the sidewalls of each of the gate structure. Multiple second spacers are formed on the sidewalls of each of the isolation structure. A dielectric layer is formed on the substrate. Then, a self-aligned process is performed to form multiple contact openings in the dielectric layer between the gate structures. The conductive material is filled in the contact openings.

Abstract: A method of fabricating conductive lines is described. A substrate having a polysilicon layer thereon is provided. A mask layer having an opening that exposes the polysilicon layer is formed on the polysilicon layer. Then, spacers are formed on the sidewalls of the mask layer. Using the mask layer and the spacers as a mask, a portion of the polysilicon layer is removed until the substrate is exposed. After that, an insulating layer that completely fills the opening is formed over the substrate. The insulating layer has an etching selectivity different from the mask layer. Thereafter, the mask layer is removed to expose the polysilicon layer and then a metal silicide layer is formed on the upper surface of the polysilicon layer.

Abstract: A method for forming a trench gate dielectric layer is described. First, a substrate having a trench therein is provided. An in-situ steam generated oxidation process is performed to form a sacrificial layer on the surface of the trench. Then, the sacrificial layer is removed. Next, a low-pressure chemical vapor deposition is performed to form a gate dielectric layer on the surface of the trench.

Abstract: A flash memory cell and a method for fabricating the same are described. The flash memory cell comprises a substrate, a select gate, a floating gate, a gate dielectric layer, a high-voltage doped region and a source region. The substrate has a first opening thereon and a second opening in the first opening. The select gate is on the sidewall of the first opening, and the floating gate is on the sidewall of the second opening. The gate dielectric layer is between the select/floating gate and the substrate. The high-voltage doped region is in the substrate under the second opening, and the source region is in the substrate beside the first opening. In the method of fabricating the flash memory cell, the select gate and the floating gate are simultaneously formed on the side walls of the first opening and the second opening, respectively.

Abstract: A method of manufacturing an non-volatile memory device is provided herein. A substrate is provided and then a trench is formed in the substrate. Thereafter, a bottom oxide layer, a charge-trapping layer and a top oxide layer are sequentially formed over the substrate and the surface of the trench. A conductive layer is formed over the top oxide layer filling the trench. The conductive layer is patterned to form a gate over the trench. The top oxide layer, the charge-trapping layer and the bottom oxide layer outside the gate are removed. A source/drain doping process is carried out. Because the non-volatile memory device is manufactured within the trench, storage efficiency of the device is improved through an increase in the coupling ratio. Furthermore, more charges can be stored by increasing the depth of the trench.

Abstract: A method for fabricating self-aligned conductive lines is provided. A substrate with a plurality of isolation structures is provided. The isolation structures are protrusive from the surface of the substrate, and an active region is defined between two adjacent isolation structures. A plurality of semiconductor devices is formed in the active region. A conductive material layer is then formed on the substrate. Thereafter, a portion of the conductive material layer is removed by using the isolation structures as a removing-stop layer until the surfaces of the isolation structures are exposed and a plurality of conductive lines are formed in a self-aligned manner to electrically connect devices. As the size of the devices is scaled down, the design rule of the lithography process does not limit the size of self-aligned conductive lines. Consequently, the fabricated conductive lines are capable of effectively connecting the semiconductor devices.

Abstract: A method of manufacturing semiconductor devices having self-aligned contacts is provided. Multiple isolation structures are formed on the substrate to define an active area. Multiple gate structures are formed on the substrate. Multiple doped areas are formed in the substrate beside each gate structure. Multiple first spacers are formed on the sidewalls of each of the gate structure. Multiple second spacers are formed on the sidewalls of each of the isolation structure. A dielectric layer is formed on the substrate. Then, a self-aligned process is performed to form multiple contact openings in the dielectric layer between the gate structures. The conductive material is filled in the contact openings.

Abstract: A non-volatile memory device and method of manufacturing the same is provided. A substrate is provided and then a trench is formed in the substrate. Thereafter, a bottom oxide layer, a charge-trapping layer and a top oxide layer are sequentially formed over the substrate and the surface of the trench. A conductive layer is formed over the top oxide layer filling the trench. The conductive layer is patterned to form a gate over the trench. The top oxide layer, the charge-trapping layer and the bottom oxide layer outside the gate are removed. A source/drain doping process is carried out. Because the non-volatile memory device is manufactured within the trench, storage efficiency of the device is improved through an increase in the coupling ratio. Furthermore, more charges can be stored by increasing the depth of the trench.

Abstract: A method of fabricating conductive lines is described. A substrate having a polysilicon layer thereon is provided. A mask layer having an opening that exposes the polysilicon layer is formed on the polysilicon layer. Then, spacers are formed on the sidewalls of the mask layer. Using the mask layer and the spacers as a mask, a portion of the polysilicon layer is removed until the substrate is exposed. After that, an insulating layer that completely fills the opening is formed over the substrate. The insulating layer has an etching selectivity different from the mask layer. Thereafter, the mask layer is removed to expose the polysilicon layer and then a metal silicide layer is formed on the upper surface of the polysilicon layer.

Abstract: A method for forming a trench gate dielectric layer is described. First, a substrate having a trench therein is provided. An in-situ steam generated oxidation process is performed to form a sacrificial layer on the surface of the trench. Then, the sacrificial layer is removed. Next, a low-pressure chemical vapor deposition is performed to form a gate dielectric layer on the surface of the trench.

Abstract: A non-volatile memory device and method of manufacturing the same is provided. A substrate is provided and then a trench is formed in the substrate. Thereafter, a bottom oxide layer, a charge-trapping layer and a top oxide layer are sequentially formed over the substrate and the surface of the trench. A conductive layer is formed over the top oxide layer filling the trench. The conductive layer is patterned to form a gate over the trench. The top oxide layer, the charge-trapping layer and the bottom oxide layer outside the gate are removed. A source/drain doping process is carried out. Because the non-volatile memory device is manufactured within the trench, storage efficiency of the device is improved through an increase in the coupling ratio. Furthermore, more charges can be stored by increasing the depth of the trench.