Patents by Inventor Han-Ping Chen
Han-Ping Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11972810Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected word lines. The memory cells are disposed in strings and configured to retain a threshold voltage. A control means is configured to apply a program voltage to selected ones of the word lines while applying pass voltages to unselected ones of the word lines and ramp down both the selected ones of the plurality of word lines and the unselected ones of the word lines to a recovery voltage at a start of a verify phase of each of a plurality of program loops and apply a targeted word line bias to each of the word lines during the verify phase. The control means is also configured to adjust the recovery voltage based on the targeted word line bias applied to each of the plurality of word lines during the verify phase.Type: GrantFiled: June 21, 2022Date of Patent: April 30, 2024Assignee: SanDisk Technologies, LLCInventors: Han-Ping Chen, Wei Zhao, Henry Chin
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Publication number: 20240087650Abstract: A storage device is disclosed herein. The storage device comprises: a non-volatile memory, where the non-volatile memory includes a block of N wordlines partitioned into a plurality of sub-blocks; and control circuitry coupled to the N wordlines. The control circuitry is configured to: determine a program status of an unselected sub-block of the plurality of sub-blocks before performing an operation on a selected sub-block of the plurality of sub-blocks; based on determining that the program status of the unselected sub-block is programmed, perform a precharge operation including applying a first precharge time; and based on determining that the program status of the unselected sub-block is not programmed, perform a precharge operation including applying a second precharge time, wherein the first precharge time is for a longer period than the second precharge time.Type: ApplicationFiled: September 8, 2022Publication date: March 14, 2024Applicant: SanDisk Technologies LLCInventors: Han-Ping Chen, Guirong Liang
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Publication number: 20240079062Abstract: The memory device includes at least one memory block with source and drain sides and a plurality of memory cells arranged in a plurality of word lines. The word lines are arranged in a plurality of independently programmable and erasable sub-blocks. Control circuitry is configured to program the memory cells of a selected sub-block and determine a location of the within the at least one memory block and determine a programming condition of at least one unselected sub-block. The control circuitry is also configured to program at least one word line in the selected sub-block in a plurality of program loops that include pre-charging processes. The control circuitry pre-charges a plurality of channels from either the source or drain side based on at least one of the location of the selected sub-block within the memory block and the programming condition of the at least one unselected sub-block.Type: ApplicationFiled: September 6, 2022Publication date: March 7, 2024Applicant: SanDisk Technologies LLCInventors: Jiacen Guo, Han-Ping Chen, Henry Chin, Guirong Liang, Xiang Yang
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Publication number: 20240079063Abstract: The memory device includes a memory block, which includes a plurality of memory cells arranged in a plurality of word lines. The memory device also includes control circuitry in communication with the memory block. The control circuitry is configured to perform a programming operation to program the memory cells of a selected word line of the plurality of word lines. During the programming operation, the control circuitry is configured to apply a programming pulse VPGM to a selected word line to the selected word line, apply a first pass voltage to a first set of word lines of the plurality of word lines, the first set of word lines being adjacent the selected word line, and apply a second pass voltage to a second set of word lines of the plurality of word. The first pass voltage is greater than the second pass voltage.Type: ApplicationFiled: September 7, 2022Publication date: March 7, 2024Applicant: SanDisk Technologies LLCInventors: Han-Ping Chen, Yanjie Wang
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Patent number: 11854620Abstract: An apparatus is provided that includes a plurality of word lines that include a plurality of word line zones, a plurality of non-volatile memory cells coupled to the plurality of word lines, and a control circuit coupled to the non-volatile memory cells. The control circuit is configured to determine a corresponding initial program voltage for each of the word line zones. Each corresponding initial program voltage is determined based on a number of program erase cycles.Type: GrantFiled: June 18, 2021Date of Patent: December 26, 2023Assignee: SanDisk Technologies LLCInventors: Erika Penzo, Han-Ping Chen, Henry Chin
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Publication number: 20230410920Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected word lines. The memory cells are disposed in strings and configured to retain a threshold voltage. A control means is configured to apply a program voltage to selected ones of the word lines while applying pass voltages to unselected ones of the word lines and ramp down both the selected ones of the plurality of word lines and the unselected ones of the word lines to a recovery voltage at a start of a verify phase of each of a plurality of program loops and apply a targeted word line bias to each of the word lines during the verify phase. The control means is also configured to adjust the recovery voltage based on the targeted word line bias applied to each of the plurality of word lines during the verify phase.Type: ApplicationFiled: June 21, 2022Publication date: December 21, 2023Applicant: SanDisk Technologies LLCInventors: Han-Ping Chen, Wei Zhao, Henry Chin
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Publication number: 20220406380Abstract: An apparatus is provided that includes a plurality of word lines that include a plurality of word line zones, a plurality of non-volatile memory cells coupled to the plurality of word lines, and a control circuit coupled to the non-volatile memory cells. The control circuit is configured to determine a corresponding initial program voltage for each of the word line zones. Each corresponding initial program voltage is determined based on a number of program erase cycles.Type: ApplicationFiled: June 18, 2021Publication date: December 22, 2022Applicant: SanDisk Technologies LLCInventors: Erika Penzo, Han-Ping Chen, Henry Chin
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Publication number: 20220392551Abstract: Apparatus and methods are described to program memory cells and control bit line discharge schemes during programming based on the data pattern. The memory controller can predict program data pattern based on SLC pulse number and TLC data completion signals and use these signals to adjust when the inhibited bit lines can discharge. Once a TLC program operation have more one data, the memory controller will enable EQVDDSA_PROG to equalize to VDDSA, and then discharge. In SLC program, the memory controller will enable EQVDDSA_PROG only in first program pulse and disable it thereafter.Type: ApplicationFiled: June 2, 2021Publication date: December 8, 2022Applicant: SanDisk Technologies LLCInventors: Hua-Ling Hsu, Henry Chin, Han-Ping Chen, Erika Penzo, Fanglin Zhang
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Patent number: 11521691Abstract: Apparatus and methods are described to program memory cells and control bit line discharge schemes during programming based on the data pattern. The memory controller can predict program data pattern based on SLC pulse number and TLC data completion signals and use these signals to adjust when the inhibited bit lines can discharge. Once a TLC program operation have more one data, the memory controller will enable EQVDDSA_PROG to equalize to VDDSA, and then discharge. In SLC program, the memory controller will enable EQVDDSA_PROG only in first program pulse and disable it thereafter.Type: GrantFiled: June 2, 2021Date of Patent: December 6, 2022Assignee: SanDisk Technologies LLCInventors: Hua-Ling Hsu, Henry Chin, Han-Ping Chen, Erika Penzo, Fanglin Zhang
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Patent number: 11139031Abstract: A storage device is disclosed herein. The storage device comprises a block including a plurality of memory cells and a circuit coupled to the plurality of memory cells of the block. The circuit is configured to determine data states for a first set of memory cells of a neighboring word line of the set of word lines, determine a bit line voltage bias and a sense time for a memory cell of a second set of memory cells of the selected word line based on a data state determined for a memory cell for each memory cell of the second set of memory cells, and perform a verify operation on the selected word line using the bit line voltage bias and the sense time determined for each memory cell of the second set of memory cells.Type: GrantFiled: June 17, 2020Date of Patent: October 5, 2021Assignee: SanDisk Technologies LLCInventors: Han-Ping Chen, Guirong Liang, Henry Chin
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Patent number: 10964402Abstract: Techniques are described for reprogramming memory cells to tighten threshold voltage distributions and improve data retention. In one aspect, the memory cells of a word line WLn are reprogrammed after programming of memory cells of an adjacent, later-programmed word line WLn+1. The reprogramming can be limited to lower state memory cells of WLn which are adjacent to lower state memory cells of WL+1. A program pulse magnitude used in the reprogramming can be tailored to the data states of the WLn memory cell and the adjacent, WLn+1 memory cell. In some cases, the program pulse magnitudes can be grouped to reduce the implementation complexity and time. The reprogramming can occur after an initial program operation has completed, during an idle time of a control circuit.Type: GrantFiled: February 19, 2020Date of Patent: March 30, 2021Assignee: SanDisk Technologies LLCInventors: Han-Ping Chen, Henry Chin, Ashish Baraskar
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Patent number: 10957394Abstract: Apparatuses and techniques are described for pre-charging NAND string channels in a pre-charge phase of a program operation. In one aspect, a hole-type pre-charge process is used at the source end of a NAND string, where a bottom of the NAND string is connected to a p-well of a substrate. By applying a positive voltage to the p-well and a lower voltage, such as 0 V or a negative voltage, to the source-side select gate transistors and the memory cells, the holes from the p-well are injected into the channel In another approach, the hole-type pre-charge process and an electron-type pre-charge process are used sequentially in separate time periods. In another approach, the hole-type pre-charge process is used at the source end of a NAND string while the electron-type pre-charge process is used at the drain end of the NAND string.Type: GrantFiled: February 10, 2020Date of Patent: March 23, 2021Assignee: SanDisk Technologies LLCInventors: Han-Ping Chen, Wei Zhao, Henry Chin
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Patent number: 10636501Abstract: Techniques are described for reducing program disturb including neighbor word interference in a memory device. Voltages applied to the word lines adjacent to the selected word line WLn during program and read operations are adjusted. The adjacent word lines include WLn?1, a source-side adjacent word line of WLn, and WLn+1, a drain side adjacent word line of WLn. In one aspect, VWLn?1<VWLn+1 during the verify tests of the program operation for the data states above the lowest programmed data state and VWLn?1=VWLn+1 during the verify test for the lowest programmed data state. Also, VWLn?1<VWLn+1 during a read operation which distinguishes between the programmed data states and VWLn?1=VWLn+1 during a read operation which distinguishes between erased state and the lowest programmed data state.Type: GrantFiled: March 18, 2019Date of Patent: April 28, 2020Assignee: SanDisk Technologies LLCInventors: Han-Ping Chen, Ching-Huang Lu, Vinh Diep, Changyuan Chen
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Patent number: 10541035Abstract: Apparatuses and techniques are provided for accurately reading memory cells by compensating for lateral charge diffusion between adjacent memory cells. A selected memory cell is read with a compensation which is based on classifying the threshold voltages of adjacent memory cells into bins. In one aspect, the compensation is based on the level of the current control gate voltage of the selected word line. In another aspect, the classifying of the threshold voltages of the adjacent memory cells can be a function of temperature. In another aspect, a memory cell can be read with compensation after a previous read operation without compensation results in an uncorrectable error. In another aspect, the classifying uses more bins for a selected edge word line.Type: GrantFiled: June 28, 2018Date of Patent: January 21, 2020Assignee: SanDisk Technologies LLCInventors: Ching-Huang Lu, Han-Ping Chen, Chung-Yao Pai, Yingda Dong
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Publication number: 20200005878Abstract: Apparatuses and techniques are provided for accurately reading memory cells by compensating for lateral charge diffusion between adjacent memory cells. A selected memory cell is read with a compensation which is based on classifying the threshold voltages of adjacent memory cells into bins. In one aspect, the compensation is based on the level of the current control gate voltage of the selected word line. In another aspect, the classifying of the threshold voltages of the adjacent memory cells can be a function of temperature. In another aspect, a memory cell can be read with compensation after a previous read operation without compensation results in an uncorrectable error. In another aspect, the classifying uses more bins for a selected edge word line.Type: ApplicationFiled: June 28, 2018Publication date: January 2, 2020Applicant: SanDisk Technologies LLCInventors: Ching-Huang Lu, Han-Ping Chen, Chung-Yao Pai, Yingda Dong
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Publication number: 20070080211Abstract: A credit card payment method and system ensures the security and robustness of payment transaction processing and validation procedure by utilizing an ordered list of supplementary credit card numbers and by requiring a card holder to present said supplementary credit card numbers, one by one, according to a pre-determined selection rules for consecutive payment transactions. Said credit card payment method and system further allows a supplementary credit card number to carry information regarding the transaction payment amount to enhance the security of payment processing. Also, said method and system is cost-effective to implement and highly compatible with the current credit card payment verification procedure.Type: ApplicationFiled: October 11, 2005Publication date: April 12, 2007Inventor: Han-ping Chen
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Publication number: 20070045398Abstract: A method and system verifies the validity of a credit card payment transaction with a set of requester account data by searching an account record database for a matched record containing a record account number that matches the requester account number and an expected verification key that matches the requester verification key, said expected verification key changes after each successful payment transaction validation, according to a pre-determined list of values, and a set of pre-determined rules, to enhance the security and robustness of account transactions. Also, the present invention provides a method and system that is cost-effective to implement and highly compatible with the current account verification procedure.Type: ApplicationFiled: August 23, 2005Publication date: March 1, 2007Inventor: Han-ping Chen
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Publication number: 20070017972Abstract: A method and system verifies the validity of a credit card payment transaction with a set of requester account data by searching an account record database for a matched record containing a record account number that matches the requester account number and an expected verification key that matches the requester verification key, said expected verification key changes after each successful payment transaction validation, according to a pre-determined list of values to enhance the security and robustness of account transactions. Also, the present invention provides a method and system that is cost-effective to implement and highly compatible with the current account verification procedure.Type: ApplicationFiled: July 19, 2005Publication date: January 25, 2007Inventor: Han-ping Chen
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Patent number: 7153744Abstract: A method of manufacturing a microelectronic device including, in one embodiment, providing a substrate having a plurality of partially completed microelectronic devices including at least one partially completed memory device and at least one partially completed transistor. At least a portion of the partially completed transistor is protected by forming a first layer over the portion of the partially completed transistor to be protected during a subsequent material removal step. A second layer is formed substantially covering the partially completed memory device and the partially completed transistor. Portions of the second layer are removed leaving a portion of the second layer over the partially completed memory device. At least a substantial portion of the first layer is removed from the partially completed transistor after the portions of the second layer are removed.Type: GrantFiled: April 12, 2004Date of Patent: December 26, 2006Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Han-Ping Chen, Chung-Yi Yu
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Publication number: 20060007196Abstract: A method and apparatus performs position-oriented adjustments of panel control signals for a flat panel display device in order to correct or compensate for pixel, line, or area defects or distortions such that the display quality meets or approaches a specification level. Also, the present invention provides a method to reduce the adjustment parameter storage by using simplified parametric descriptions.Type: ApplicationFiled: June 4, 2004Publication date: January 12, 2006Inventor: Han-Ping Chen