Abstract: A synchronizing circuit (SC) is proposed which recovers from input data (ID) applied thereto a data clock signal (DC) synchronous therewith in frequency and in phase. The circuit (SC) consists of a tuned tapped delay line (TDL) generating a plurality of mutually delayed local clock signals (DCS), a latching circuit (SM) sampling these delayed local clock signals at input data level transitions thereby providing sampled versions (LCSV) thereof as well as a comparator (C1) pairwise comparing said delayed local clock signals with respective ones of the sampled versions. It can be verified that with such a circuit the level transitions of the appropriate data clock signal (DC) are generated at the outputs of the comparator (C1) when the latter drives its output high only if a sufficient number of its pairwise comparisons hold.