Abstract: A method of forming surface planarity to a substrate during removal of excess dielectric material when fabricating recessed regions of dielectric material in a semiconductor device wherein a dielectric layer is formed on the surface of the silicon substrate, a relatively thick layer of polycrystalline silicon deposited over the SiO.sub.2 layer, openings formed through the polycrystalline layer and SiO.sub.2 layer and into the substrate to form trenches, vapor depositing a layer of dielectric material over the surface of the substrate to a depth sufficient to fill the trench, depositing a planarized layer over a layer of dielectric material, reactive ion etching the planarizing layer, the dielectric layer, the polycrystalline layer, and selectively removing the remaining polycrystalline silicon layer to expose the SiO.sub.2 layer.

Abstract: A method for making lateral PNP or NPN devices in isolated monocrystalline silicon pockets wherein silicon dioxide isolation surrounds the pocket and partially, below the surface, within the isolated monocrystalline region. The P emitter or N emitter diffusion is made over the portion of the silicon dioxide that partially extends into the monocrystalline isolated pocket. This structure reduces the vertical current injection which will give relatively high (beta) gain even at low base to emitter voltages. The lateral PNP or NPN device resulting from the method is in a monocrystalline silicon pocket wherein silicon dioxide isolation surrounds the pocket and partially, below the surface, within the isolated monocrystalline silicon region. The P emitter or N emitter diffusion is located over the portion of the silicon dioxide that partially extends into the monocrystalline isolated pocket.

Abstract: A method for forming a narrow dimensioned, for example, submicron, region on a silicon body that involves forming on the silicon body regions having substantially horizontal surfaces and substantially vertical surfaces. A layer of a very narrow dimension is formed both on the substantially horizontal and substantially vertical surfaces. Reactive ion etching is applied to the layer to substantially remove the horizontal layer while leaving the vertical layer substantially intact. The vertical layer dimension is adjusted depending upon the original thickness of the layer applied.

Abstract: Lateral PNP or NPN devices in isolated monocrystalline silicon pockets wherein silicon dioxide isolation surrounds the pocket and partially, below the surface, within the isolated monocrystalline region are described. The P emitter or N emitter diffusion is made over the portion of the silicon dioxide that partially extends into the monocrystalline isolated pocket. This structure reduces the vertical current injection which will give relatively high (beta) gain even at low base to emitter voltages.

Abstract: A method for producing deeply recessed oxidized regions in silicon. A series of deep trenches are formed in a silicon wafer by a reactive ion etching (RIE) method. In a first species, the trenches are of equal width. A block-off mask is selectively employed during part of the RIE process to produce trenches of unequal depth. The trench walls are thermally oxidized to completely fill in all of the trenches with oxide at the same time. In a second species, the trenches are of equal depth and width and of uniform spacing. In one aspect of the second species, the width of the trenches is equal to the distance between the trenches whereby the thermal oxidation completely fills in the trenches with oxide at the same time that the silicon between the trenches is fully converted to silicon oxide.