Abstract: An integrated semiconductor memory includes a parallel test device and block groups. The parallel test device is used for writing in and evaluating data to be written into and read out of the semiconductor memory. Several groups of memory cells can be simultaneously tested for operation in a test mode, with each group being disposed along a respective word line. The data read out during the process can be evaluated by the parallel test device. The result of the evaluation is present, separately for each group of memory cells, on I/O data lines of the semiconductor memory. The semiconductor memory can also have redundant memory cells, in which case defective memory cells or groups of memory cells can be replaced in connection with the test mode.

Abstract: An integrated semiconductor memory includes a memory cell field having memory cells disposed in matrix form, word lines and internal bit lines forming pairs of internal bit lines for triggering the memory cells. Internal weighting circuits are each assigned to a respective one of the internal bit line pairs. An external pair of bit lines is commonly assigned to the internal bit lines. Pairs of separation transistors are each assigned to a respective one of the internal bit line pairs for electrical separation of the respective internal bit line pair from the external pair of bit lines. A bit line decoder triggers the pairs of separation transistors. An external weighting circuit is provided. A discriminator device and a precharging device are connected to the external bit line pair. The internal bit lines of each pair of internal bit lines are triggered separately from one another.