Abstract: A vector e-beam machine for random defect inspection is disclosed. Contrary to traditional wisdom, it is shown that through a careful choice of target locations, vector machines can provide high-throughput and high coverage even when scanning for random defects. Additionally, by not wastefully scanning locations that provide no additional fault observability, charge accumulation on the wafer—a major concern in e-beam scanning—is reduced. In a preferred embodiment, two approaches are combined: 1) Scan/target only at locations where a random failure can be observed. 2) From the defined list of observable locations, scan/target only the points which have the highest efficiency. Use of these and/or other disclosed techniques enables the scanner to target and evaluate a majority of the total observable defects in a single pass.

Abstract: An IC that includes a contiguous standard cell area with a 4x3 e-beam pad that is compatible with advanced manufacturing processes and an associated e-beam testable structure.

Abstract: An IC that includes a contiguous standard cell area with a 4×3 e-beam pad that is compatible with advanced manufacturing processes and an associated e-beam testable structure.

Abstract: An IC that includes a contiguous standard cell area with a 4×3 e-beam pad that is compatible with advanced manufacturing processes and an associated e-beam testable structure.

Abstract: An IC that includes a contiguous standard cell area with a 4×3 e-beam pad that is compatible with advanced manufacturing processes and an associated e-beam testable structure.

Abstract: An IC that includes a contiguous standard cell area with a 4×3 e-beam pad that is compatible with advanced manufacturing processes and an associated e-beam testable structure.

Abstract: An IC that includes a contiguous standard cell area with a 4×3 e-beam pad that is compatible with advanced manufacturing processes and an associated e-beam testable structure.

Abstract: A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, corner short, and via open test areas.

Abstract: An IC includes a contiguous standard cell area with first, second, and third TS-GATE-short-configured test area geometries disposed therein. In some embodiments, the contiguous standard cell area may further include: fourth and fifth TS-GATE-short-configured test area geometries, and/or other test area geometries, such as tip-to-tip-short, tip-to-side-short, diagonal-short, corner-short, interlayer-overlap-short, via-chamfer-short, merged-via-short, snake-open, stitch-open, via-open, or metal-island-open.

Abstract: Improved processes for manufacturing wafers, chips, or dies utilize in-line data obtained from non-contact electrical measurements (“NCEM”) of fill cells that contain structures configured target/expose a variety of open-circuit, short-circuit, leakage, or excessive resistance failure modes. Such processes may involve evaluating Designs of Experiments (“DOEs”), comprised of multiple NCEM-enabled fill cells, in at least two variants, all targeted to the same failure mode(s).

Abstract: A method is disclosed for designing a test vehicle utilizing a layout of a real integrated circuit (IC) product. The method comprises: importing an original full-chip layout of the real IC product; partitioning the original full-chip layout into probe groups, each probe group comprising probe pads, and, a plurality of IC devices within an area of interest (AOI) having original routing interconnect for those IC devices; selecting a set of IC devices within the AOI; and, for the selected set of IC devices, using pattern extraction to remove the original routing interconnect, and create customized interconnect layers (CIL) to reconfigure connection between the individual IC devices. Incorporating the selected set of IC devices with the CIL into the original full-chip layout creates a modified full-chip layout such that a wafer fabricated using the modified full-chip layout comprises a real product with a built-in test vehicle.

Abstract: A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective tip-to-tip short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with a moving stage and beam deflection to account for motion of the stage.

Abstract: An IC includes first and second designs of experiments (DOES), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The first DOE contains fill cells configured to enable non-contact (NC) detection of tip-to-side shorts, and the second DOE contains fill cells configured to enable NC detection of corner shorts.

Abstract: A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one side-to-side short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side short, and side-to-side short test areas.

Abstract: A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one corner short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side short, and corner short test areas.

Abstract: A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, chamfer short, and corner short test areas.

Abstract: A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one chamfer short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, chamfer short, and via open test areas.

Abstract: A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one side-to-side short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, side-to-side short, and via open test areas.

Abstract: A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one chamfer short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective chamfer short, corner short, and via open test areas.

Abstract: A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of a resistance through a stitch, where such measurements are obtained by scanning a pad comprised of at least three electrically connected, parallel conductive stripes using a moving stage with beam deflection to account for motion of the stage.