Abstract: A chip having a substrate region having a substrate contact, an RS latch having two complementary nodes representing a storage state of the RS latch, a control circuit having a control input and configured to connect one of the complementary nodes to a supply potential depending on a potential at the control input, wherein the control input is connected to the substrate contact, and an output circuit connected to an output of the RS latch and configured to trigger an alarm depending on the storage state of the RS latch.

Abstract: A chip having a substrate region having a substrate contact, an RS latch having two complementary nodes representing a storage state of the RS latch, a control circuit having a control input and configured to connect one of the complementary nodes to a supply potential depending on a potential at the control input, wherein the control input is connected to the substrate contact, and an output circuit connected to an output of the RS latch and configured to trigger an alarm depending on the storage state of the RS latch.

Abstract: A chip having a substrate region having a substrate contact, an RS latch having two complementary nodes representing a storage state of the RS latch, a control circuit having a control input and configured to connect one of the complementary nodes to a supply potential depending on a potential at the control input, wherein the control input is connected to the substrate contact, and an output circuit connected to an output of the RS latch and configured to trigger an alarm depending on the storage state of the RS latch.

Abstract: A chip having a substrate region having a substrate contact, an RS latch having two complementary nodes representing a storage state of the RS latch, a control circuit having a control input and configured to connect one of the complementary nodes to a supply potential depending on a potential at the control input, wherein the control input is connected to the substrate contact, and an output circuit connected to an output of the RS latch and configured to trigger an alarm depending on the storage state of the RS latch.

Abstract: A microprocessor circuit for organizing access to data or programs stored in a memory has a microprocessor, a memory for storing an operating system, and a memory for storing individual external programs. A plurality of memory areas with respective address spaces is provided in the memory for storing the external programs. Each address space is assigned an identifier. The identifier assigned to a memory area is loaded into a first auxiliary register prior to the addressing of the memory area and the identifier of the addressed memory area is loaded into a second auxiliary register. A comparison of the contents of the first and second auxiliary registers is performed. Furthermore, each address space of a memory area is assigned at least one bit sequence defining access rights, whereby code instructions and sensitive data can be protected against write accesses from other external programs.

Abstract: A microprocessor circuit for organizing access to data or programs stored in a memory has a microprocessor, a memory for storing an operating system, and a memory for storing individual external programs. A plurality of memory areas with respective address spaces is provided in the memory for storing the external programs. Each address space is assigned an identifier. The identifier assigned to a memory area is loaded into a first auxiliary register prior to the addressing of the memory area and the identifier of the addressed memory area is loaded into a second auxiliary register. A comparison of the contents of the first and second auxiliary registers is performed. Furthermore, each address space of a memory area is assigned at least one bit sequence defining access rights, whereby code instructions and sensitive data can be protected against write accesses from other external programs.