Abstract: Disclosed is a method for fabricating a contract hole plane in a memory module with an arrangement of memory cells each having a selection transistor. The methods can be utilized during the production of dynamic random access memory (DRAM) modules.

Abstract: A mark configuration for the alignment and/or determination of a relative position of at least two planes in relation to one another in a substrate and/or in layers on a substrate during lithographic exposure, in particular, in the case of a wafer during the production of DRAMs, includes a mark structure, and at least one layer of a definable thickness underneath the mark structure for adjusting the physical position of the mark structure relative to a reference plane in or on the substrate. Also provided is a wafer having such a configuration and a process for providing such a configuration. The invention allows a mark configuration to have mark structures exhibiting good contrast regardless of the design or the process conditions.

Abstract: In order to fabricate a contact hole plane in a memory module with an arrangement of memory cells each having a selection transistor, on a semiconductor substrate with an arrangement of mutually adjacent gate electrode tracks on the semiconductor surface, an insulator layer is formed on the semiconductor surface and a sacrificial layer is subsequently formed on the insulator layer, then material plugs are produced on the sacrificial layer for the purpose of defining contact openings between the mutually adjacent gate electrode tracks, the sacrificial layer is etched to form material plugs with the underlying sacrificial layer blocks, after the production of the vitreous layer with uncovering of the sacrificial layer blocks above the contact openings between the mutually adjacent gate electrode tracks, an essentially planar surface being formed, then the sacrificial layer material is etched out from the vitreous layer and the uncovered insulator material is removed above the contact openings on the semiconduct

Abstract: A mark configuration is provided for the orientation and/or determination of the relative position of a substrate and/or of layers on the substrate during a lithographic exposure, in particular for the case of a wafer during the fabrication of DRAMs. At least one part of a mark is disposed above a patterned background for the purpose of increasing a difference in contrast between the mark and the substrate. A wafer can also be manufactured with such a mark configuration. A method for fabricating the mark configuration is also described. An efficient and simple orientation of layers and/or of the substrate is thus made possible.

Abstract: A mark configuration for the alignment and/or determination of a relative position of at least two planes in relation to one another in a substrate and/or in layers on a substrate during lithographic exposure, in particular, in the case of a wafer during the production of DRAMs, includes a mark structure, and at least one layer of a definable thickness underneath the mark structure for adjusting the physical position of the mark structure relative to a reference plane in or on the substrate. Also provided is a wafer having such a configuration and a process for providing such a configuration. The invention allows a mark configuration to have mark structures exhibiting good contrast regardless of the design or the process conditions.

Abstract: A mark configuration is provided for the orientation and/or determination of the relative position of a substrate and/or of layers on the substrate during a lithographic exposure, in particular for the case of a wafer during the fabrication of DRAMs. At least one part of a mark is disposed above a patterned background for the purpose of increasing a difference in contrast between the mark and the substrate. A wafer can also be manufactured with such a mark configuration. A method for fabricating the mark configuration is also described. An efficient and simple orientation of layers and/or of the substrate is thus made possible.