Abstract: In a method for reducing detrimental phenomena related to disturb voltages in a data storage apparatus employing passive matrix addressing, particularly a memory device or a sensor device, an application of electric potentials conforming to an addressing operation is generally controlled in a time-coordinated manner according to a voltage pulse protocol. In an addressing operation a data storage cell is set to a first polarization state by means of a first active voltage pulse and then, dependent on the voltage pulse protocol, a second voltage pulse which may be a second active voltage pulse of opposite polarity to that of the first voltage pulse, is applied and used for switching the data storage cell to a second polarization state. The addressed cell is thus set to a predetermined polarization state as specified by the addressing operation.

Abstract: In a method for fabricating a memory device based on an electrically polarizable memory material in the form of an electret or ferroelectric material, the memory device comprises one or more layers with circuit structures provided exclusively or partially in a printing process. At least one protective interlayer is provided between at least two layers in the memory device, said protective interlayer exhibiting low solubility as well as low permeability for any solvents employed in the deposition of the other layers in the device. Use in fabricating a memory device, particularly a passive matrix-addressable memory device with an electret or ferroelectric memory material.

Abstract: In a method for operating a passive matrix-addressable ferroelectric or electret memory device, a voltage pulse protocol based on a 1/3 voltage selection rule is used in order to keep disturb voltages at minimum, the voltage pulse protocol comprising cycles for read and write/erase bases on time sequence of voltage pulses with defined parameters. The method comprises a refresh procedure wherein cells for refresh are selected and refresh requests processed by a memory device controller, the refresh requests are monitored and processed in regard of ongoing or scheduled memory operations, and refresh voltage pulses with defined parameters are applied to the memory cells selected for refresh, while simultaneously ensuring that non-selected memory cells are subjected to zero voltage or voltages which do not affect the polarization state of these cells.

Abstract: In an organic electronic circuit (C), particularly a memory circuit with an organic ferroelectric or electret material (2) the active material comprises fluorine atoms and consists of various organic materials. The active material is located between a first electrode and a second electrode. A cell with a capacitor-like structure is defined in the active material and can be accessed for an addressing operation via a first and a second electrode. At least one of these electrodes (1a, 1b) comprises a layer of chemically modified gold. In a passive matrix-addressable electronic device, particularly a ferroelectric or electret memory device, circuits (C) of this kind with the active material as a ferroelectric or electret memory material form the elements of a matrix-addressable array and define the memory cells provided between first and second set of addressing electrodes. At least the electrodes of at least one of the sets then comprise at least a layer of gold.

Abstract: In a heating and temperature control system for a data storage apparatus comprising at least one matrix-addressable ferroelectric or electret memory device, Joule heating means are provided in the memory device, a temperature determining means is connected with controller circuitry and the controller circuitry is connected with an external power supply, which controlled by the former powers the Joule heating means to achieve a selected operating temperature. In a method for operating the heating and temperature control system an ambient or instant temperature of the memory device is determined and compared with the set nominal optimal temperature, and the difference between these temperatures is used in a predefined algorithm for establishing control parameters for the application of power to the Joule heating means to achieve the selected operating temperature in the memory device during an addressing operation thereto.

Abstract: In a method for enhancing the data storage capability of ferroelectric or electret memory cell which has been applied to storage of data and attained an imprint condition, suitable voltage pulses are used for evoking a temporary relaxation of the imprint condition into a volatile polarization state that can be discriminated from the imprinted polarization state in a non-destructive readout operation. Sequences of one or more voltage pulses are used to evoke readout signals respectively indicative of a non-volatile and a volatile polarization state of the memory cell, but without altering said polarization states.

Abstract: An organic electronic device consists of one or more electro-active organic or polymer materials sandwiched between electrodes. Critical in such devices is the interface between the electrode and the polymer, where degradation or chemical reaction products may develop that are deleterious to the proper functioning of the device. This is solved by introducing a functional interlayer composed of one or more materials consisting of a molecular backbone bearing phosphonate or phosphate functions, either directly attached or through side chains, said functional layer being disposed between at least one of the respective electrodes and said one or more electro-active materials in the device.

Abstract: In a ferroelectret or electret memory cell a polymeric memory material is a blend of two or more ploymeric materials, the polymeric material being provided contacting first and second electrodes. Each electrode is a composite multilayer comprising a first highly conducting layer and a conducting polymer layer, the latter forming a contact between the former and the memory material.

Abstract: A matrix-addressable ferroelectric or electret memory device and a method of operating are explained. The method includes applying a first plurality of voltage difference across a first and a second set of electrodes in the memory when data are read, and applying a second plurality of voltage differences when data are refreshed or rewritten. The first and second plurality of voltage differences correspond to sets of potential levels comprising time sequences of voltage pulses. At least one parameter indicative of a change in a memory cell response is used for determining at least one correction factor for the voltage pulses, whereby the pulse parameter is adjusted accordingly. The memory device comprises means for determining the at least one parameter, a calibration memory connected with means for determining the correction factor, and control circuits for adjusting pulse parameters as applied to read and write operations in the memory device.

Abstract: A method of driving a passive matrix display or memory array of cells comprising an electrically polarizable material exhibiting hysteresis, in particular a ferroelectric material, wherein the polarization state of individual cells can be switched by application of electric potentials or voltages to word and bit lines in the matrix or array.

Abstract: In a memory and/or data processing device having at least two stacked layers which are supported by a substrate or forming a sandwich self-supporting structure, wherein the layers comprise memory and/or processing circuitry with mutual connections between the layers and/or to circuitry in the substrate, the layers are mutually arranged such that contiguous layers form a staggered structure on at least one edge of the device and at least one electrical edge conductor is provided passing over the edge on one layer and down one step at a time, enabling the connection to an electrical conductor in any of the following layers in the stack. A method for manufacturing a device of this kind comprises steps for adding said layers successively, one layer at a time such that the layers form a staggered structure and for providing one or more layers with at least one electrical contacting pad for linking to one or more interlayer edge connectors.