Abstract: Provided is a novel keeper circuit with a pull-up device whose strength changes for different operating supply levels so that the pull-up device is weaker for smaller supply levels and stringer for higher supply levels.

Abstract: Provided is a novel keeper circuit with a pull-up device whose strength changes for different operating supply levels so that the pull-up device is weaker for smaller supply levels and stringer for higher supply levels.

Abstract: In the present invention, a method is provided for analyzing signal noise caused by cross-coupling between an attacker signal line, upon which an attacker signal resides, and a victim signal line, upon which a victim signal resides. This method comprises selecting the victim signal, selecting the attacker signal, performing cross-talk attacker filtering on a plurality of signal lines to identify a first set of potential attacker signals on a first set of potential attacker signal lines that cause signal noise upon said victim signal, performing safety window filtering on a plurality of signals signal lines to identify a second set of potential attacker signals on a second set of potential attacker signal lines that cause signal noise upon the victim signal line, and reducing the effects of the signal noise on at least one of the victim signal lines.

Abstract: This invention illustrates a method is provided for analyzing cross-coupling between an attacker signal line, upon which an attacker signal resides, and a victim signal line, upon which a victim signal resides. The method in this invention comprises the acts of selecting the victim signal, selecting the attacker signal, performing timing filtering upon a number of signal lines in order to identify a set of potential attacker signals, performing logic filtering upon a number of signal lines to identify a second set of potential attacker signals, and reducing the effects of the cross-coupling between the attacker signal line and the victim signal line.

Abstract: A probe assembly for use in conveying signals between cables from test apparatus and contact areas on a contact face of an integrated circuit includes a support member having an aperture therein and a dielectric membrane clamped over the aperture such that conductive bumps mounted on the underside of the periphery of the membrane engage corresponding contact areas on an upper surface of the support member surrounding the aperture. A central area of the membrane extends downward through the aperture such that conductive bumps on the under side of the central area of the membrane engage contact areas on the contact face of an integrated circuit situated below the aperture. A plurality of conductor runs supported by the membrane extend from the conductive bumps in the central area of the membrane to the conductive bumps in the periphery of the membrane.

Abstract: A multiple port memory includes a set of memory units each comprising a set of memory cells, one corresponding to each port. Each cell of a memory unit stores a single data bit and each cell is independently read and write accessed through separate data, address and control busses. The cells of each memory unit are cross-coupled so that when the state of the bit stored by one of the cells of a memory unit is changed when write accessed, the other cells of the memory unit thereafter change the states of their stored bits in the same way.

Abstract: A clock signal is transmitted to nodes of each of several interconnected circuits through a separate adjustable delay circuit, the time delay of each delay circuit being adjusted so that the clock signal arrives at each node at the same time, thereby synchronizing operation of the separate integrated circuits one to another. Each delay circuit comprises a set of signal delay elements which can be selectively switched into the clock signal path so that the clock signal delay may be adjusted by adjusting the number of signal delay elements in the clock signal path. Each signal delay element itself has a unit delay adjustable in proportion to an applied control voltage generated by a delay element monitor. The delay element monitor measures the unit delay in relation to the period of a stable reference clock and adjusts the delay of each delay element as necessary to ensure that the unit delay remains constant.