Abstract: Disclosed is an AGC detector device and an AGC detecting method for television receivers displaying video pictures consisting of a plurality of horizontal lines to be built up successively, wherein a CVBS signal is inputted which includes horizontal sync pulses having a front porch region and a back porch region and occurring once a horizontal line during a horizontal sync period when generating a current video picture, and further includes vertical sync pulses occurring during a vertical sync period before the generation of a new video picture and including serration pulses which occur during a serration pulse region being part of the vertical sync period. Further, gating pulses are generated having a period which is equal to the line period of the horizontal sync pulses. Said gating pulses are adjusted such that they occur at the back porch region of the horizontal sync pulses.

Abstract: The invention relates to a digital phase locked loop (PLL) 12 for demodulating an intermediate frequency signal. The digital phase locked loop 12 comprises two coordinate rotation digital computers 24 and 30 in its phase detector. The robustness the PLL 12 can be improved by means of a gain control circuit 27, a sign detector 20, a carrier monitoring circuit 28 and an adjustable loop filter 32.

Abstract: A circuit arrangement includes at least one adapter circuit (10). which amplifies an analog input signal of a low current (Ii) by an amplification factor (n) into a particularly analog output signal of a higher current (Io). The adapter circuit includes an input, which corresponds to a range of low voltages (Ui); an output (18), which corresponds to a range of higher voltages (Uo); at least one npn transistor current mirror (14); and at least one pnp transistor current mirror (16) arranged in series with the npn transistor current mirror (14), and connected to at least one high voltage source (30), wherein the at least one pnp transistor current mirror amplifies the input signal, which is received from the at least one npn transistor current mirror.

Abstract: To provide a circuit arrangement, particularly for a television, multimedia, radio or video recording device, for transition from a range of low voltage (Ui) to a range of higher voltage (Uo) having a simple and low-cost structure and operating as an interface between the range of low voltage (Ui) and a range of higher voltage (Uo) in a stable and reliable way, also when the voltage difference between the range of low voltage (Ui) and the range of higher voltage (Uo) is large, it is proposed that at least one adapter circuit (10) is provided, which amplifies a particularly analog input signal of a low current (Ii) by an amplification factor (n) into a particularly analog output signal of a higher current (Io),

Abstract: In an arrangement for offset current compensation of a phase detector (4) which is provided in a phase-locked loop (2) to which an acquisition circuit (7) is assigned which, in a switch-on phase of the phase-locked loop (2), supplies acquisition pulses to a loop filter (5) arranged in the phase-locked loop (2) before applying an input signal to the phase-locked loop (2) so as to bring the operating frequency of a controllable oscillator (6) in the phase-locked loop within a predetermined frequency window, the arrangement (1) determines an offset correction current during at least one time interval of the switch-on phase when acquisition pulses occur, which offset correction current serves for compensating the offset current of the phase detector (4), the value and the sign of the offset correction current being selected in dependence upon the rate and sign of the acquisition pulses in such a way that no acquisition pulses occur any longer at the end of the switch-on phase, and in that the arrangement (1) supe