Patents by Inventor Hans Joakim Bangs

Hans Joakim Bangs has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatus and method for instant on ability
    Patent number: 10320215
    Abstract: In an embodiment, a system includes voltage sensing logic to determine a first source voltage Vfirst source corresponding to a first source, and a controller to receive an indication of Vfirst source from the voltage sensing logic. The controller is to, responsive to Vfirst source>a first output voltage (V1), select a first source first regulator to input Vfirst source and provide V1; responsive to Vfirst source>a second output voltage (V2), select a first source second voltage regulator that inputs Vfirst source, and provide V2; responsive to Vfirst source?V1, select a second source first voltage regulator that inputs a second source voltage Vsecond source that corresponds to a second source and is substantially constant in time where Vsecond source>V1, and provide V1 independent of the first source first regulator and the first source second voltage regulator. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventors: Viacheslav Suetinov, Hans Joakim Bangs, Nicholas P. Cowley, Mark S. Mudd, Ruchir Saraswat, Richard J. Goldman
  • Digital phase controlled delay circuit
    Patent number: 9741405
    Abstract: An adjustable phase clock generator circuit is described that may include a DLL and a phase adjustor to further adjust the phase of a selected clock phase from the DLL. Both the DLL and phase adjustor may be formed from current starved delay elements that are biased from a common bias generator circuit.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: August 22, 2017
    Assignee: Intel Corporation
    Inventors: Viacheslav Suetinov, Hans Joakim Bangs, Philip P. Hackney
  • Apparatus and Method for Instant On Ability
    Publication number: 20170093174
    Abstract: In an embodiment, a system includes voltage sensing logic to determine a first source voltage Vfirst source corresponding to a first source, and a controller to receive an indication of Vfirst source from the voltage sensing logic. The controller is to, responsive to Vfirst source>a first output voltage (V1), select a first source first regulator to input Vfirst source and provide V1; responsive to Vfirst source>a second output voltage (V2), select a first source second voltage regulator that inputs Vfirst source, and provide V2; responsive to Vfirst source?V1, select a second source first voltage regulator that inputs a second source voltage Vsecond source that corresponds to a second source and is substantially constant in time where Vsecond source>V1, and provide V1 independent of the first source first regulator and the first source second voltage regulator. Other embodiments are described and claimed.
    Type: Application
    Filed: September 25, 2015
    Publication date: March 30, 2017
    Inventors: VIACHESLAV SUETINOV, HANS JOAKIM BANGS, NICHOLAS P. COWLEY, MARK S. MUDD, RUCHIR SARASWAT, RICHARD J. GOLDMAN
  • DIGITAL PHASE CONTROLLED DELAY CIRCUIT
    Publication number: 20160359491
    Abstract: An adjustable phase clock generator circuit is described that may include a DLL and a phase adjustor to further adjust the phase of a selected clock phase from the DLL. Both the DLL and phase adjustor may be formed from current starved delay elements that are biased from a common bias generator circuit.
    Type: Application
    Filed: June 14, 2016
    Publication date: December 8, 2016
    Inventors: Viacheslav Suetinov, Hans Joakim Bangs, Philip P. Hackney
  • DIGITAL PHASE CONTROLLED DELAY CIRCUIT
    Publication number: 20160182061
    Abstract: An adjustable phase clock generator circuit is described that may include a DLL and a phase adjustor to further adjust the phase of a selected clock phase from the DLL. Both the DLL and phase adjustor may be formed from current starved delay elements that are biased from a common bias generator circuit.
    Type: Application
    Filed: December 19, 2014
    Publication date: June 23, 2016
    Applicant: Intel Corporation
    Inventors: Viacheslav SUETINOV, Hans Joakim Bangs, Philip Hackney
  • Digital phase controlled delay circuit
    Patent number: 9369136
    Abstract: An adjustable phase clock generator circuit is described that may include a DLL and a phase adjustor to further adjust the phase of a selected clock phase from the DLL. Both the DLL and phase adjustor may be formed from current starved delay elements that are biased from a common bias generator circuit.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: June 14, 2016
    Assignee: Intel Corporation
    Inventors: Viacheslav Suetinov, Hans Joakim Bangs, Philip Hackney