Abstract: The invention relates to a method for the selective silicidation of contact areas that allow the production of highly integrated circuits, preferably in a SMOS or BiCMOS process. To this end, a metal oxide layer (14) that contains for example praseodymium oxide is deposited onto a prepared wafer (12). A silicon layer (16) and on top of said silicon layer a cover layer (18) is deposited onto the metal oxide layer (14), said cover layer being laterally structured. In a subsequent tempering step in an oxygen-free, reducing gas atmosphere the silicon layer (16) and the metal oxide layer (14) are converted to a metal silicide layer in lateral sections (20, 22) in which the cover layer (18) was previously removed.

Abstract: An electronic component is disclosed having a first layer of metallically conductive material, a second layer of semiconductor material, and a third layer between the first and second layers. The third layer comprises a dielectric and at least inhibits charge carrier transport both from the first to the second layer and also from the second to the first layer. The dielectric comprises praseodymium oxide of the form Pr2O3 in predominantly single crystal phase, and the second layer comprises silicon with a (001)- or with a (111)-crystal orientation at an interface with the third-layer.

Abstract: A silicon-germanium hetero bipolar transistor comprising a silicon collector layer, a boron-doped silicon-germanium base layer, a silicon emitter layer and an emitter contact area. The transistor is fabricated using an epitaxy process on a surface of pure silicon. An electrically inert material is incorporated into the epitaxial layers in order to link the defects in the semiconductor structure and to reduce the outdiffusion of the dopant. Thus, a transistor for high-frequency applications can be fabricated in two ways: to increase the dopant dose of the base region or to reduce the thickness of the base layer. In particular, the concentration profile of germanium in the base layer has a general shape of a triangle or trapezoid.

Abstract: A silicon-germanium hetero bipolar transistor comprising a silicon collector layer, a boron-doped silicon-germanium base layer, a silicon emitter layer and an emitter contact area. The transistor is fabricated using an epitaxy process on a surface of pure silicon. An electrically inert material is incorporated into the epitaxial layers in order to link the defects in the semiconductor structure and to reduce the outdiffusion of the dopant. Thus, a transistor for high-frequency applications can be fabricated in two ways: to increase the dopant dose of the base region or to reduce the thickness of the base layer. In particular, an implantation or doped region having a T-shaped cross section profile is provided between the emitter layer and the emitter contact area.

Abstract: A silicon-germanium hetero bipolar transistor comprising a silicon collector layer, a boron-doped silicon-germanium base layer, a silicon emitter layer and an emitter contact area. The transistor is fabricated using an epitaxy process on a surface of pure silicon. An electrically inert material is incorporated into the epitaxial layers in order to link the defects in the semiconductor structure and to reduce the outdiffusion of the dopant. Thus, a transistor for high-frequency applications can be fabricated in two ways: to increase the dopant dose of the base region or to reduce the thickness of the base layer. In particular, carbon is incorporated in the base layer and in the collector layer and/or emitter layer.

Abstract: The invention concerns an electronic component with a first layer (16) of metallically conductive material, a second layer (12) of semiconductor material and a third layer (14) between the first (16) and second (12) layers, wherein the third layer (14) includes a dielectric and is adapted to inhibit or prevent charge carrier transport both from the first to the second layer and also from the second to the first layer. According to the invention the dielectric contains praseodymium oxide in predominantly single crystal phase. 1 Berlin 25 Jul.

Abstract: The invention relates to a MOSFET with a doped silicon source layer and a doped polycrystalline silicon gate layer and a doped silicon drain layer and to a method of fabricating the layers of such a transistors, in which an otherwise possible interaction between closely spaced layers or structural components of decreased size is eliminated or at least substantially reduced by incorporation in at least one layer of the MOSFET of an element from Group IV in a predetermined concentration.