Abstract: An apparatus and method for generating a modified video signal consisting of a correction signal and a video input signal. The correction signal is derived from a digitized video input signal by at least a frequency-band limiter and an amplitude limiter. The video input signal is delayed by the processing time of the correction signal before the two signals are combined. To avoid unwanted harmonics the amplitude limiter uses a transfer function which can be exactly described by a rational integral function of the nth degree,y=a.sub.0 +a.sub.1 *x+a.sub.2 *x.sup.2 +a.sub.3 *x.sup.3 . . . a.sub.n *x.sup.nwith 1<n<f.sub.n /f.sub.s, where f.sub.n is the Nyquist frequency, f.sub.s is the maximum frequency of the frequency-band-limited video signal, x is the input to the amplitude limiter a.sub.0 to a.sub.n are scale factors, and y is the output of the amplitude limiter.

Abstract: A limiter circuit responds to an input signal which has a plurality of frequencies within a given band. The input signal is split up into two frequency ranges by means of a low pass filter for one range and a high pass filter for a second range. The output of the low pass filter is directed to a first limiter while the output of the high pass filter is directed to a variable notch filter. The outputs from the first limiter and the notch filter are added together to provide a sum signal. The sum signal is applied to a second limiter which performs limiting strictly according to the amplitude. The outputs of the second limiter signal provide the desired signal and a control signal to determine how often the second limiter is limiting. The control signal varies the attenuation of the notch filter. In this manner frequencies, within a selective range and which will be otherwise effected by the spurious frequencies generated during limiting, are reduced.

Abstract: An arrangement and method for reducing the noise component of a television picture chrominance signal, using a vertical digital filter. A noise-reduced reference signal is formed from the chrominance signals of vertically preceding lines. A difference signal is derived, wherein the noise-reduced reference signal, entering into the calculation of the difference signal, is created by the recursive signal processing operations of the digital filter. The transversal signal-processing operations of the digital filter affects the reduction of the noise component. The difference signal, before passing through the recursive and transversal signal-processing operations, is applied to a limiter. The limiter introduces an amplitude-dependent attenuation to obtain a modified difference signal. The modified difference signal enters into the recursive and transversal signal-processing operations instead of the original difference signal.

Abstract: A digital phase-locked loop has a periodically overflowing digital oscillator (DCO), implemented as a modulo adder, and a processor device. The processor device adjusts the period T of the digital oscillator to a nominal period, determined from periodically occurring synchronizing pulses, by comparing the actual phase of the digital oscillator with a set phase at the control clock rate of the periodic synchronizing pulses. After the digital oscillator has been locked to the nominal period, the processor device compares the phases by using a double-frequency signal sequence of one-half line period derived from the digital oscillator output signal. The DCO output signal is fed to a correction device where an address-phase signal, locked to the DCO output signal, is generated so that when a non-periodic synchronizing pulse occurs, the address-phase signal is shifted by one period of the signal sequence of one-half line period with respect to the digital oscillator output signal.

Abstract: A digital television-signal-processing circuit for a composite color signal is sampled with a first clock signal. The digitized composite color signal is reconverted with a line-locked second clock signal. The two clock signals have the same frequency. A second phase-locked loop for controlling the phase of the horizontal pulse includes a locked oscillator and is loosely coupled to a first phase-locked loop which generates a horizontal reference clock. The decoupling of the data, which is referred to the two clock signals, takes place in a dual-port read/write memory which is written into synchronously with the first clock signal and read from synchronously with the second clock signal.