Abstract: A method of forming matched PFET/NFET spacers with differential widths for SG and EG structures and a method of forming differential width nitride spacers for SG NFET and SG PFET structures and PFET/NFET EG structures and respective resulting devices are provided. Embodiments include providing PFET SG and EG structures and NFET SG and EG structures; forming a first nitride layer over the substrate; forming an oxide liner; forming a second nitride layer on sidewalls of the PFET and NFET EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the PFET SG and EG structures; forming RSD structures on opposite sides of each of the PFET SG and EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the NFET SG and EG structures; and forming RSD structures on opposite sides of each of the NFET SG and EG structures.

Abstract: A semiconductor device is disclosed including a gate electrode structure and raised drain and source regions that extend to a first height level and a sidewall spacer element positioned adjacent the sidewalls of the gate electrode structure between the raised drain and source regions and the gate electrode structure. The sidewall spacer element includes an upper portion that extends above the first height level wherein an inner part of the spacer element faces the gate electrode structure and extends to a second height level that is less than a third height level of an outer part of the upper portion of the spacer element.

Abstract: The present disclosure relates to manufacturing techniques and respective semiconductor devices in which the capping material of gate electrode structures may be removed together with portions of the capping material of resistors on the basis of a highly controllable directional etch process, wherein raised drain and source regions may be protected on the basis of a fill material.

Abstract: The present disclosure relates to manufacturing techniques and respective semiconductor devices in which the capping material of gate electrode structures may be removed together with portions of the capping material of resistors on the basis of a highly controllable directional etch process, wherein raised drain and source regions may be protected on the basis of a fill material.

Abstract: A semiconductor device structure is disclosed including a semiconductor-on-insulator (SOI) substrate, the SOI substrate comprising a semiconductor layer, a substrate material and a buried insulating material layer positioned between the semiconductor layer and the substrate material, a trench isolation structure positioned in at least a portion of the SOI substrate, the trench isolation structure defining a first region in the SOI substrate, and a capacitor device formed in the first region, the capacitor device comprising a first electrode formed by a conductive layer portion formed in the first region on the buried insulating material layer, the conductive layer portion at least partially replacing the semiconductor layer in the first region, a second electrode formed over the first electrode, and an insulating material formed between the first electrode and the second electrode.

Abstract: A method of manufacturing a semiconductor device is provided including providing an SOI substrate comprising a semiconductor bulk substrate, a buried insulation layer and a semiconductor layer, forming a shallow trench isolation in the SOI substrate, forming a FET in and over the SOI substrate, and forming a contact to a source or drain region of the FET that is positioned adjacent to the source or drain region, wherein forming the shallow trench isolation includes forming a trench in the SOI substrate, filling a lower portion of the trench with a first dielectric layer, forming a buffer layer over the first dielectric material layer, the buffer layer having a material different from a material of the first dielectric layer, and forming a second dielectric layer over the buffer layer and of a material different from the material of the buffer layer.

Abstract: A method of manufacturing a complementary metal-oxide-semiconductor (CMOS) device comprising an N-type metal-oxide-semiconductor (NMOS) region and a P-type metal-oxide-semiconductor (PMOS) region is provided, that comprises: depositing a raised source and drain (RSD) layer of a first type in the NMOS region and the PMOS region at the same time; selectively removing the RSD layer of the first type in one of the NMOS region and the PMOS region; and depositing an RSD layer of a second type in the one of the NMOS region and the PMOS region.

Abstract: A transistor element of a sophisticated semiconductor device includes a gate electrode structure including a metal-containing electrode material instead of the conventionally used highly doped semiconductor material. The metal-containing electrode material may be formed in an early manufacturing stage, thereby reducing overall complexity of patterning the gate electrode structure in approaches in which the gate electrode structure is formed prior to the formation of the drain and source regions. Due to the metal-containing electrode material, high conductivity at reduced parasitic capacitance may be achieved, thereby rendering the techniques of the present disclosure as highly suitable for further device scaling.

Abstract: A method of forming a semiconductor device includes providing a silicon-on-insulator substrate comprising a semiconductor bulk substrate, a buried insulation layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried insulation layer, providing at least one N-type metal-oxide semiconductor gate structure being an NZG gate structure having a gate insulation layer over the semiconductor layer and at least one P-type metal-oxide semiconductor gate structure being a PZG gate structure having a gate insulation layer over the semiconductor layer, the NZG and PZG gate structures being electrically separated from each other.

Abstract: The present disclosure provides a method of forming a semiconductor device structure including forming a first gate stack comprising a first gate dielectric material and a first gate electrode material over a first active region in an upper portion of a substrate, forming a first spacer structure adjacent to the first gate stack, and forming first raised source/drain (RSD) regions at opposing sides of the first gate stack on the first active region in alignment with the first spacer structure. Herein, forming the first spacer structure includes forming a first spacer structure on sidewalls of the first gate stack, the first gate dielectric extending in between the first spacer and the upper surface portion, patterning the first gate dielectric material, and forming a second spacer over the first spacer and the patterned first gate dielectric material.

Abstract: The present disclosure provides a method of forming a semiconductor device structure including forming a first gate stack comprising a first gate dielectric material and a first gate electrode material over a first active region in an upper portion of a substrate, forming a first spacer structure adjacent to the first gate stack, and forming first raised source/drain (RSD) regions at opposing sides of the first gate stack on the first active region in alignment with the first spacer structure. Herein, forming the first spacer structure includes forming a first spacer structure on sidewalls of the first gate stack, the first gate dielectric extending in between the first spacer and the upper surface portion, patterning the first gate dielectric material, and forming a second spacer over the first spacer and the patterned first gate dielectric material.

Abstract: A semiconductor device structure is disclosed including a semiconductor-on-insulator (SOI) substrate, the SOI substrate comprising a semiconductor layer, a substrate material and a buried insulating material layer positioned between the semiconductor layer and the substrate material, a trench isolation structure positioned in at least a portion of the SOI substrate, the trench isolation structure defining a first region in the SOI substrate, and a capacitor device formed in the first region, the capacitor device comprising a first electrode formed by a conductive layer portion formed in the first region on the buried insulating material layer, the conductive layer portion at least partially replacing the semiconductor layer in the first region, a second electrode formed over the first electrode, and an insulating material formed between the first electrode and the second electrode.

Abstract: A method of forming a semiconductor device includes providing a silicon-on-insulator substrate comprising a semiconductor bulk substrate, a buried insulation layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried insulation layer, providing at least one N-type metal-oxide semiconductor gate structure being an NZG gate structure having a gate insulation layer over the semiconductor layer and at least one P-type metal-oxide semiconductor gate structure being a PZG gate structure having a gate insulation layer over the semiconductor layer, the NZG and PZG gate structures being electrically separated from each other.

Abstract: A method of forming matched PFET/NFET spacers with differential widths for SG and EG structures and a method of forming differential width nitride spacers for SG NFET and SG PFET structures and PFET/NFET EG structures and respective resulting devices are provided. Embodiments include providing PFET SG and EG structures and NFET SG and EG structures; forming a first nitride layer over the substrate; forming an oxide liner; forming a second nitride layer on sidewalls of the PFET and NFET EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the PFET SG and EG structures; forming RSD structures on opposite sides of each of the PFET SG and EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the NFET SG and EG structures; and forming RSD structures on opposite sides of each of the NFET SG and EG structures.

Abstract: A method of forming matched PFET/NFET spacers with differential widths for SG and EG structures and a method of forming differential width nitride spacers for SG NFET and SG PFET structures and PFET/NFET EG structures and respective resulting devices are provided. Embodiments include providing PFET SG and EG structures and NFET SG and EG structures; forming a first nitride layer over the substrate; forming an oxide liner; forming a second nitride layer on sidewalls of the PFET and NFET EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the PFET SG and EG structures; forming RSD structures on opposite sides of each of the PFET SG and EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the NFET SG and EG structures; and forming RSD structures on opposite sides of each of the NFET SG and EG structures.

Abstract: A method of forming matched PFET/NFET spacers with differential widths for SG and EG structures and a method of forming differential width nitride spacers for SG NFET and SG PFET structures and PFET/NFET EG structures and respective resulting devices are provided. Embodiments include providing PFET SG and EG structures and NFET SG and EG structures; forming a first nitride layer over the substrate; forming an oxide liner; forming a second nitride layer on sidewalls of the PFET and NFET EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the PFET SG and EG structures; forming RSD structures on opposite sides of each of the PFET SG and EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the NFET SG and EG structures; and forming RSD structures on opposite sides of each of the NFET SG and EG structures.

Abstract: A semiconductor device includes an SOI substrate and a transistor device positioned in and above the SOI substrate. The SOI substrate includes a semiconductor bulk substrate, a buried insulation layer above the semiconductor bulk substrate, and a semiconductor layer above the buried insulation layer. The transistor device includes a gate structure having a gate electrode and a first cap layer covering upper and sidewall surfaces of the gate electrode. An oxide liner covers sidewalls of the gate structure and a second cap layer covers the oxide liner. A recess is located adjacent to the gate structure and is at least partially defined by an upper surface of the semiconductor layer, a bottom surface of the second cap layer and at least part of the oxide liner. Raised source/drain regions are positioned above the semiconductor layer and portions of the raised source/drain regions are positioned in the recess.

Abstract: The present disclosure provides a method of forming a semiconductor device, including a shaping of a gate structure of the semiconductor device such that a spacer removal after silicide formation is avoided and silicide overhang is suppressed. In some aspects of the present disclosure, a method of forming a semiconductor device is provided wherein a gate structure is provided over an active region of a semiconductor substrate, the gate structure including a gate electrode material and sidewall spacers. At least one of the gate electrode material and the sidewall spacers are shaped by applying a shaping process to the gate structure and a silicide portion is formed on the shaped gate structure.

Abstract: A semiconductor structure including a nonvolatile memory cell element including an active region formed in a semiconductor material, a select gate structure, a dummy control gate structure and a transfer gate structure is provided. Additionally, an electrically insulating structure extending around each of the select gate structure, the dummy control gate structure and the transfer gate structure is provided. The dummy control gate structure is removed, wherein a first recess is formed in the semiconductor structure. After removing the dummy gate structure, a charge trapping layer and a layer of a control gate electrode material are deposited over the semiconductor structure. Portions of the charge trapping layer and the layer of the control gate electrode material over the electrically insulating structure are removed. Portions of the charge trapping layer and the layer of control gate electrode material in the recess provide a control gate structure of the nonvolatile memory cell.

Abstract: A semiconductor structure includes a nonvolatile memory cell including a first nonvolatile bit storage element and a second nonvolatile bit storage element which have a common source region provided in a semiconductor material and a common control gate structure. Each nonvolatile bit storage element includes a drain region, a channel region, a select gate structure, a floating gate structure and an erase gate structure. The channel region has a select gate side portion and a floating gate side portion. The select gate structure is provided at the select gate side portion of the channel region and the floating gate structure is provided at the floating gate side portion of the channel region. The erase gate structure is provided above the select gate structure and adjacent the floating gate structure. The control gate structure extends above the floating gate structures of the first and second nonvolatile bit storage elements.