Abstract: A digital waveform synthesizer (1) is implemented as a single chip integrated circuit on a single chip (2) and comprises a direct digital synthesizer (10) which produces a synthesized output signal waveform on an output terminal (4) which is substantially phase and frequency locked to the phase and frequency of an externally generated input signal applied to an input terminal (5).

Abstract: A digital waveform synthesiser (1) is implemented as a single chip integrated circuit on a single chip (2) and comprises a direct digital synthesiser (10) which produces a synthesised output signal waveform on an output terminal (4) which is substantially phase and frequency locked to the phase and frequency of an externally generated input signal applied to an input terminal (5).

Abstract: A digital waveform synthesiser (1) is implemented as a single chip integrated circuit on a single chip (2) and comprises a direct digital synthesiser (10) which produces a synthesised output signal waveform on an output terminal (4) which is substantially phase and frequency locked to the phase and frequency of an externally generated input signal applied to an input terminal (5).

Abstract: A single chip digital frequency synthesiser (1) for synthesising a frequency swept synthesised output signal of a selectable frequency sweep comprises a direct digital synthesiser (5) which produces the frequency swept synthesised output signal on an output terminal (7) in response to values of a frequency control digital word applied to a frequency control input (8) thereof by an on-chip data processing circuit (25). An on-chip programmable data storing circuit (12) is programmable to store data indicative of a selected mode in which the digital frequency synthesiser (1) is to operate, and to store data indicative of selectable frequency and the time domains of the frequency swept synthesised output signal to be produced.

Abstract: A digital-to-analogue converter (DAC) (1) comprises a digital processing circuit (2) having an input register (10) to which data samples of a digital input signal are written at a data sampling rate (fs). A delay register (14) holds each data sample for one clock cycle of the data sampling rate (fs), and a subtracting circuit (15) sequentially produces difference values between consecutive ones of the data samples by subtracting the data sample in the delay register (14) from the input register (12) on each clock cycle of the data sampling rate (fs).

Abstract: “A compensating circuit for use in a switch circuit comprising scaled current steering switches, a switch circuit comprising the compensating circuit, and a method for minimising time-skew in switching scaled current steering switches” An eight bit current steering DAC comprising scaled current steering switches (ST0,SF0,ST(n−1),SF(n−1)) (where n=8) comprises a comprising plurality of compensating MOS switches (SCT0 and SCF0 to SCT(n−1) for minimising time-skew when switching selected ones of the current steering switches from one state to another. The compensating switches (SCT,SCF) are of type similar to the current steering switches (STi and SFi), and are sized so that the combined switching load presented to the corresponding driver circuit (Di) by the sum of the parasitic load capacitance of the current steering switch (STi or SFi) and the corresponding compensating switch (SCTi or SCFi) is substantially similar for each driver circuit (Di).

Abstract: An eight bit current steering DAC comprising scaled current steering switches (ST0,SF0,ST(n−1),SF(n−1)) (where n=8) comprises a scaled load compensating circuit (12) comprising a plurality of compensating MOS switches (SCT0 and SCF0 to SCT(n−1) to SCF(n−1)). The compensating switches (SCT,SCF) are of type similar to the current steering switches (ST1 and SFi), and are sized so that the combined switching load presented to the corresponding driver circuit D1 by the sum of the parasitic load capacitance of the current steering switches (ST1 or SF1) and the corresponding parasitic switching load capacitance of the corresponding compensating switch (SCTi or SCF1) is substantially similar for each driver circuit D1. Additionally, by virtue of the fact that the switching load capacitance, and in turn the switching loads presented to the driver circuits (D1) are similar, the driver circuits (D1) are therefore also similar to each other.

Abstract: A Digital-to-Analog (D/A) converter with programmable transfer function includes a Main Converter and at least one Sub-Converter. Errors in the Main Converter are compensated for by programming the one or more Sub-Converters with compensation values determined during a Calibration Sequence. The Calibration Sequence measures the deviations of the transfer function of the Main Converter from the ideal at predetermined bit transitions of the digital input signal and generates representative separate digital signals for the one or more Sub-Converters. By combining these separate signals with the digital input signal, the net errors of the D/A Converter transfer function are reduced.