Abstract: A reduced instruction set computer processor, having a rapid access, dual port register file for supplying operands to a high speed arithmetic logic unit, is implemented as a set of integrated circuits interconnected by constant impedance transmission lines and synchronized by a common clock signal. The transmission lines interconnecting the integrated circuits are formed by thin metallic foil conductors separated by dielectric polyimide membranes. The clock signal is adjustably delayed prior to transmission to each integrated circuit so that pulses of the clock signal arrive at each integrated circuit at the same time regardless of differences in inherent delays of the separate paths the clock signal must follow to each integrated circuit.