Abstract: In the configuration, the module can “learn” one or more time intervals from the external tester and then repeat them internally or compare them to its own internally measured time intervals, for instance, for the purpose of evaluating whether the module in question has crossed a time specification value or remains below the value. The module can also measure and store one or more internal time intervals and transmit them to the external tester in digital or analog form.

Abstract: The memory device of a semiconductor chip is tested with a BIST circuit. The configuration and the method store the test results obtained by the BIST circuit. The test results are stored in the sense amplifiers of the memory device. In addition, it also possible for test programs for the BIST circuit to be stored in the sense amplifiers.

Abstract: An integrated circuit incorporating a self-test device and a method for producing a self-testing integrated circuit. The integrated circuit has a program memory with at least one external terminal for loading external test programs. The integrated circuit has a self-test device connected to the program memory, the self-test device executing program commands of a test program loaded into the program memory, the program commands succeeding one another in address terms, for carrying out a self-test of the circuit. The self-test device has an interrupt signal input, through which the self-test device interrupts the test program that is currently being executed by not executing the respective succeeding program command in address terms. Rather, it executes a program jump within the test program, the program jump being triggered by the interrupt signal.

Abstract: In a module with a BIST function to which signal pulses are fed from outside with a tester, a configuration for generating signal impulses of defined lengths includes registers configured to store measured pulse lengths, and a variable delay element configured to measure pulse lengths of externally supplied signal pulses in a training phase. The element has a series circuit of inverters and delay-free signal paths parallel thereto for read/write from/into the registers. AND gates are disposed between a delay-free write signal path and the element and behind an even number of respective inverters, and the output of the AND gates are connected to the registers through the decoder. AND gates are disposed between the delay-free read signal path and the element and behind an even number of respective inverters. One input of the AND gates is connected to the registers through the decoder, another input is connected to the element, and the outputs are connected to the delay-free read signal path.