Abstract: A semiconductor device includes a substrate, a first sheet pattern on the substrate, a gate electrode on the substrate and surrounding the first sheet pattern, a first source/drain pattern and a second source/drain pattern respectively connected to a first end and a second end of the first sheet pattern, a contact blocking pattern on a lower side of the second source/drain pattern, a first source/drain contact extending in a first direction and connected to the first source/drain pattern, and a second source/drain contact connected to the second source/drain pattern and extending in the first direction to contact an upper surface of the contact blocking pattern. A depth from an upper surface of the gate electrode to a lowermost portion of the first source/drain contact may be greater than a depth from the upper surface of the gate electrode to the upper surface of the contact blocking pattern.

Abstract: According to an embodiment, a display device may include a display panel which may include a display area and a non-display area. The display panel may include a first subpixel including a first light emitting area, a second subpixel including a second light emitting area, a third subpixel including a third light emitting area, a sensor pixel including a light sensing area, a pixel defining layer separating the first through third light emitting areas and the light sensing area, and a partition wall disposed on the pixel defining layer to surround the sensor pixel.

Abstract: A method of monitoring and managing performance of an artificial neural network model for an air interface may comprise: receiving, by a network (NW) including a communication node performing a function of monitoring and managing performance of an artificial neural network model, a performance metric of the artificial neural network model from a user equipment (UE); and controlling, by the communication node, activation or deactivation of the artificial neural network model according to the performance metric, wherein the artificial neural network model is activated to improve a main performance metric of a mobile communication system including the communication node and the UE connected through an air interface.

Abstract: A transistor array substrate includes a substrate, an active layer disposed on the substrate and including a channel region, a source region and a drain region, a gate insulating layer disposed on a part of the active layer, a gate electrode overlapping the channel region of the active layer and included in an electrode conductive layer which is disposed on the gate insulating layer, a source electrode included in the electrode conductive layer and in contact with a part of the source region of the active layer, and a drain electrode included in the electrode conductive layer and in contact with a part of the drain region of the active layer. The active layer includes an oxide semiconductor including crystals and is disposed as an island shape excluding a hole in a plan view.

Abstract: An electronic assembly is provided. The electronic assembly includes a first circuit structure including a conductive structure, a second circuit structure disposed on the first circuit structure, a plurality of electronic elements disposed on the first circuit structure, and a connecting element disposed on the first circuit layer. The connecting element is disposed between two adjacent ones of the plurality electronic elements and electrically connected to the second circuit layer and one of the two adjacent ones of the plurality of electronic elements.

Abstract: A display device includes a data conductive layer including a first power line, a passivation layer with a first opening exposing the first power line, a via layer with a second opening partially overlapping the first opening, a pixel electrode on the via layer, a connection electrode in the first and second openings, a pixel-defining film with an opening overlapping the second opening, a light-emitting layer on the pixel-defining film, the pixel electrode and the connection electrode, and a common electrode connected to the first power line. The data conductive layer includes a data base layer, a data main metal layer, and a data capping layer, the first power line includes a wire connection structure, in which the data main metal layer is recessed from sides of the data capping layer, and the common electrode is connected to the data main metal layer in the wire connection structure.

Abstract: The present disclosure provides a method for treating liver cirrhosis by using a composition including mesenchymal stem cells, extracellular vesicles produced by the mesenchymal stem cells, and growth factors. The composition of the present disclosure achieves the effect of treating liver cirrhosis through various efficacy experiments.

Abstract: A method for processing contents at an electronic device is provided. The method includes generating a first content corresponding to a user input applied to content via the electronic device, and displaying a floating user interface (UI), which displays first scrap information on the first content, on a screen of the electronic device.

Abstract: A semiconductor package includes a first semiconductor die and a second semiconductor die disposed laterally adjacent one another. The semiconductor package includes a semiconductor bridge overlapping a first corner of the first semiconductor die and a second corner of the second semiconductor die. The semiconductor bridge electrically couples the first semiconductor to the second semiconductor die. The semiconductor package includes a third semiconductor die and a fourth semiconductor die electrically coupled to the first semiconductor die and the second semiconductor die, respectively. The semiconductor bridge is interposed between the third semiconductor die and the fourth semiconductor die.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.

Abstract: A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.

Abstract: A semiconductor device includes a first stack structure, a second stack structure, and a third stack structure. Each of the stack structure includes semiconductor layers vertically spaced from one another. The first, second, and third stack structures all extend along a first lateral direction. The second stack structure is disposed between the first and third stack structures. The semiconductor device includes a first gate structure that extends along a second lateral direction and wraps around each of the semiconductor layers. The semiconductor layers of the first stack structure are coupled with respective source/drain structures. The semiconductor layers of the second stack structure are coupled with respective source/drain structures. The semiconductor layers of the third stack structure are coupled with a dielectric passivation layer.

Abstract: A switch control circuit and a switch control method are provided. In this circuit, compositions that sense a drain voltage of a switch device are added in a QR Buck Converter switch control circuit. A first resistor, a second switch, a second resistor are electrically connected to a drain terminal of a switch device to sense the 0 A state of an inductor current. On the basis of a detection result, the switch control circuit turns on the switch device when an inductor current is 0 A, and a drain sensing voltage (ZCD) is less than a predetermined reference voltage (REF).

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, and a source/drain (S/D) region adjacent to the gate structure. The S/D region can include first and second side surfaces separated from each other. The S/D region can further include top and bottom surfaces between the first and second side surfaces. A first separation between the top and bottom surfaces can be greater than a second separation between the first and second side surfaces.

Abstract: A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide a method for manufacturing a semiconductor device, and a semiconductor device produced thereby, that comprises an interposer without through silicon vias.

Abstract: A network-on-chip (NoC) system includes a default communication path between a master device and a slave device, and a backup communication path between the master device and the slave device. The default communication path is configured to work in a normal operation state of the chip. The backup communication path is configured to replace the default communication path when a fault arises in the default communication path.

Abstract: The present invention provides a latching guide structure arranged inside a door of semiconductor carrier. The latching guide structure comprises an upper latching part, a lower latching part, at least one elastic unit and a driver. Moreover, a first guiding portion of the upper latching part is matched with a second guiding portion of the lower latching part, therefore to define the installation space for the at least one elastic unit. On the other hand, the driver simultaneously actuates an upper actuating unit of the first guiding portion and a lower actuating unit of the second guiding portion to linearly move in reverse direction therebetween. The range of the linear motion of the upper actuating unit and the lower actuating unit represents the compression or extension of the at least one elastic unit, determining to control the open/close status of the upper latching part and the lower latching part.

Abstract: A method for making a semiconductor structure includes: providing a substrate with a contact feature thereon; forming a dielectric layer on the substrate; etching the dielectric layer to form an interconnect opening exposing the contact feature; forming a metal layer on the dielectric layer and outside of the contact feature; and forming a graphene conductive structure on the metal layer, the graphene conductive structure filling the interconnect opening, being electrically connected to the contact feature, and having at least one graphene layer that extends in a direction substantially perpendicular to the substrate.

Abstract: A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.

Abstract: A method for manufacturing a gas diffusion layer for a fuel cell wherein carbon nanotubes are impregnated into Korean paper, thereby enhancing electroconductivity, and a gas diffusion layer manufactured thereby. The method for manufacturing a gas diffusion layer for a fuel cell which is to manufacture a gas diffusion layer as a constituent member of a unit cell in a fuel cell, includes a support preparation step of preparing a support with Korean paper; a dispersion preparation step of dispersing a carbon substance in a solvent to form a dispersion, a coating step of coating the support with the dispersion, and a thermal treatment step of thermally treating the dispersion-coated support to fix the carbon substance to the support.