Abstract: A capacitive touchpad is provided, which includes a substrate module, a plurality of sensing electrodes, a plurality of driving electrodes and a plurality of light-emitting diode (LED) dies. The plurality of sensing electrodes and the plurality of driving electrodes form a touch sensing region of the capacitive touchpad, and the touch sensing region is divided into a plurality of sensing units having same areas. Each of the LED dies is arranged in two adjacent ones of the plurality of sensing units, and a position of each of the LED dies corresponds to one of the plurality of driving electrodes, and the LED dies are electrically isolated from the plurality of sensing electrodes and the plurality of driving electrodes.

Abstract: A resin composition includes 100 parts by weight of hydrocarbon resin polymers and 0.01 to 50 parts by weight of divinyl aromatic compound. A substrate structure includes a resin layer and a conductive layer disposed on the resin layer, wherein the resin layer is formed from the resin composition. A manufacturing method of the resin composition includes the following steps: providing a mixture, wherein the mixture includes a monovinyl aromatic compound and a divinyl aromatic compound, and optionally includes a bridged ring compound; polymerizing the mixture to form a crude composition; and purifying the crude composition to prepare the resin composition.

Abstract: A method for the surface treatment of a corrosion-resistant nickel-based alloy and the resulting surface structure of the treated alloy is disclosed. The method includes immersing a nickel-based alloy in a first neutral or alkaline solution to remove surface contaminants, followed by immersing the cleaned alloy in a second neutral or alkaline solution to form functional groups on its surface. Subsequently, a low-temperature heat treatment is performed to form a passivation layer on the surface of the nickel-based alloy. The passivation layer has a surface roughness of less than 0.04 microns and a thickness ranging from 5 nanometers to 200 nanometers. The resulting corrosion-resistant nickel-based alloy comprises a substrate made of the nickel-based alloy and a passivation layer established on at least one surface of the substrate. The nickel content of the alloy is greater than 50%, and the alloy may also contain additional metallic components such as chromium (Cr) and manganese (Mn).

Abstract: A mechanical key component and a mechanical keyboard are provided. The mechanical key component includes a circuit board, an elastic element and a key cap. The circuit board is provided with a first sensing electrode. The elastic element is disposed on the circuit board, and a movable portion of the elastic element is connected to a second sensing electrode. The key cap is movably disposed on the elastic element. The elastic element enables the key cap to move between an unpressed position and a pressed position, and the movable portion drives the second sensing electrode to move relative to the first sensing electrode. In response to the key cap being moved between the unpressed position and the pressed position, a coupling capacitance between the first sensing electrode and the second sensing electrode changes to indicate whether the key cap is in the unpressed position or the pressed position.

Abstract: An electronic device includes an outer case, a circuit substrate, a thermopile sensor chip, a filter structure, and a waterproof structure. The outer case has an opening. The circuit substrate is disposed inside the outer case. The thermopile sensor chip is disposed on the circuit substrate. The filter structure is disposed above the thermopile sensor chip. The waterproof structure is surroundingly connected between the filter structure and the outer case, wherein the waterproof structure has a through hole for exposing the filter structure and communicated with the opening of the outer case.

Abstract: A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure with a fin top surface disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, a gate structure disposed on the fin top surface, and a gate spacer with first and second spacer portions disposed between the gate structure and the S/D region. The first spacer portion extends above the fin top surface and is disposed along a sidewall of the gate structure. The second spacer portion extends below the fin top surface and is disposed along a sidewall of the S/D region.

Abstract: Method to implement heat dissipation multilayer and reduce thermal boundary resistance for high power consumption semiconductor devices is provided. The heat dissipation multilayer comprises a first crystalline layer that possesses a first phonon frequency range, a second crystalline layer that has a second phonon frequency range which does not overlap with the first phonon frequency range, and an amorphous layer located between the first and second crystalline layers. The amorphous layer has a third phonon frequency range that overlaps both the first and second phonon frequency ranges.

Abstract: A midsole includes a midsole body and a resilient plate disposed in the midsole body in a manner that the resilient plate extends along a longitudinal direction. The resilient plate includes a plurality of resilient tubular elements that are integrally connected to each other along the longitudinal direction. Each of the resilient tubular elements extends along a width direction perpendicular to the longitudinal direction. A shoe includes an upper, an outsole, and the aforementioned midsole which is connected between the upper and the outsole.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate; a dielectric layer on the substrate; isolation structures extending through the dielectric layer into the substrate; and a floating gate on the dielectric layer and between the isolation structures, wherein the floating gate includes a first portion directly on the dielectric layer; and second portions on the sidewalls of the first portion.

Abstract: Some embodiments relate to an IC device, including a first chip comprising a plurality of pixel blocks respectively including one of a first plurality of conductive pads, the plurality of pixel blocks arranged in rows extending in a first direction and columns extending in a second direction perpendicular to the first direction; a second chip bonded to the first chip at a bonding interface, where the second chip comprises a second plurality of conductive pad recessed and contacting the first plurality of conductive pads along the bonding interface; and a first corrugated shield line having outermost edges set-back along the second direction from outermost edges of a first row of the plurality of pixel blocks, the first corrugated shield line being arranged within a first dielectric layer and laterally separating neighboring ones of the first plurality of conductive pads within the first row of the plurality of pixel blocks.

Abstract: A semiconductor structure including a device wafer, a carrier structure, and a redistribution layer (RDL) structure is provided. The device wafer includes a first substrate, a first dielectric layer, first bonding pads, and a power via structure. The carrier structure includes the following components. A second substrate has a third surface and a fourth surface opposite to each other. A second dielectric layer is located on the third surface. Second bonding pads are located in the second dielectric layer. The second bonding pads are bonded to the first bonding pad, and the second dielectric layer is bonded to the first dielectric layer. A heat dissipation plate is located on the fourth surface. Through-substrates via (TSVs) pass through the second substrate. The TSV is electrically connected to the heat dissipation plate and the second bonding pad. The RDL structure is electrically connected to the power via structure.

Abstract: A ferroelectric memory structure including a substrate, a ferroelectric capacitor structure, and a switch device is provided. The ferroelectric capacitor structure is disposed on the substrate. The ferroelectric capacitor structure includes at least one first electrode, first dielectric layers, a second electrode, and a ferroelectric material layer. The at least one first electrode and the first dielectric layers are alternately stacked. The second electrode penetrates through the first electrode. The ferroelectric material layer is disposed between the first electrode and the second electrode. The switch device is electrically connected to the ferroelectric capacitor structure.

Abstract: Disclosed herein are pigment compositions for meat substitutes and meat substitutes including such pigment compositions. The pigment compositions include a non-heme iron-binding protein. The pigment compositions provide a pink and/or red color to a meat substitute composition. For example, the non-heme iron-binding protein my include a sequence at least 60%, at least 70%, at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, or at least 99% identical to at least one of SEQ ID NOs: 1-31.

Abstract: Provided are a memory device and a method of manufacturing the same. The memory device includes: a stack structure; a first source/drain region and a second source/drain region located in a substrate beside the stack structure; a first self-aligned contact connected to the first source/drain region; a second self-aligned contact connected to the second source/drain region; a first liner structure located between the first self-aligned contact and a first sidewall of the stack structure; and a second liner structure located between the second self-aligned contact and a second sidewall of the stack structure. The first liner structure and the second liner structure are not connected and do not cover the stack structure.

Abstract: A method and an apparatus for integrated circuit testing are provided. The method includes: operating a tester to perform a qualitative testing on devices in the integrated circuit by following electrical addresses of the devices, and to introduce an original verification pattern during the qualitative testing, such that a verification pattern corresponding to the original verification pattern can be converted from a raw data of a result of the qualitative testing; converting the raw data to a test graph presented by physical addresses, by using pre-determined scramble equations; and identifying portions of the verification pattern appeared in the test graph and comparing the portions of the verification pattern with corresponding portions of the original verification pattern by pattern recognition, and correcting the pre-determined scramble equations according to comparison result.

Abstract: A method and an apparatus for integrated circuit testing are provided. The method includes: operating a tester to perform a qualitative testing on devices in the integrated circuit by following electrical addresses of the devices, and to introduce an original verification pattern during the qualitative testing, such that a verification pattern corresponding to the original verification pattern can be converted from a raw data of a result of the qualitative testing; converting the raw data to a test graph presented by physical addresses, by using pre-determined scramble equations; and identifying portions of the verification pattern appeared in the test graph and comparing the portions of the verification pattern with corresponding portions of the original verification pattern by pattern recognition, and correcting the pre-determined scramble equations according to comparison result.

Abstract: Provided are a memory device and a method of manufacturing the same. The memory device includes: a stack structure; a first source/drain region and a second source/drain region located in a substrate beside the stack structure; a first self-aligned contact connected to the first source/drain region; a second self-aligned contact connected to the second source/drain region; a first liner structure located between the first self-aligned contact and a first sidewall of the stack structure; and a second liner structure located between the second self-aligned contact and a second sidewall of the stack structure. The first liner structure and the second liner structure are not connected and do not cover the stack structure.

Abstract: An ambient light sensor includes a substrate, a metasurface disposed on the substrate, and an aperture layer disposed on the substrate. The metasurface includes a plurality of nanostructures and a filling layer laterally surrounding the plurality of nanostructures. The aperture layer laterally separates the metasurface into a plurality of sub-meta groups.

Abstract: The method of forming the semiconductor structure includes the following steps. First trenches and second trenches are respectively formed in a substrate of the logic region and the substrate of the array region. A dielectric liner is formed in the first trenches and second trenches. First coating blocks and second coating blocks are respectively formed in the first trenches and second trenches. A cap layer is formed on the first coating blocks and the second coating blocks. Oxide structures are formed on the cap layer. Part of the oxide structures and part of the cap layer is removed. A semiconductor layer is formed in the array region and disposed on the substrate and between the oxide structures.

Abstract: A bead product is provided. The bead product comprises a plurality of beads, each of the plurality of beads having a first surface facing a first direction opposing a second surface facing a second direction; a plurality of holding members, one of the plurality of holding members disposed within or attached to the plurality of beads; a framework formed from the holding member and the plurality of beads, the framework having a first configuration and a second configuration; and a locking mechanism, the locking mechanism locks positions of the holding member, the plurality of beads or both on the framework in the first configuration and the locking mechanism unlocks only a predetermined bead of the plurality beads for movement on the framework in the second configuration. Systems and methods are disclosed.