Abstract: A semiconductor device and method of manufacturing a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a semiconductor layer located on the substrate; at least one shallow trench and at least one deep trench. Each of the at least one shallow trench and the at least one deep trench extending from a first major surface of the semiconductor layer. Sidewall regions and base regions of the trenches comprise a doped trench region and the trenches are at least partially filled with a conductive material contacting the doped region. The shallow trenches terminate in the semiconductor layer and the deep trench terminates in the semiconductor substrate.

Abstract: A common mode choke comprising a first planar coil for receiving a first signal, a second planar coil for receiving a second signal, the first and second coils comprising substantially mirror images of one another and arranged side by side in a common plane, the first planar coil and second planar coil electromagnetically coupled by a closed coupling loop.

Abstract: A semiconductor device and a method of making the same. The device includes a substrate comprising a major surface and a backside. The device also includes a dielectric partition for electrically isolating a first part of the substrate from a second part of the substrate. The dielectric partition extends through the substrate from the major surface to the backside.

Abstract: Various aspects of the disclosure are directed to circuitry that may be used to shunt current. As may be consistent with one or more embodiments a first circuit has a plurality of alternating p-type and n-type semiconductor regions with respective p-n junctions therebetween, arranged between an anode end and a cathode end. A second (e.g., bypass) circuit is connected to one of the alternating p-type and n-type semiconductor regions, and forms a further p-n junction therewith. The second circuit operates to provide carrier flow, which influences operation of the first circuit.

Abstract: An apparatus includes a first inductive component connected in series with a first signal line of a differential signal path and configured to suppress residual electrostatic discharge (ESD) current spikes on the first signal line by using a first effective inductance. A second inductive component is connected in series to a second signal line of the differential signal path configured to suppress residual ESD current spikes on a second signal line of the differential signal path by using a second effective inductance. The first and second inductive components are configured to pass differential signals on the differential signal path by using inductive coupling between the first and second inductive components to provide a third effective inductance.

Abstract: A method of making a plurality of semiconductor devices comprising a chip scale packages. The method includes providing a semiconductor wafer having a major surface and a backside. The method also includes forming a plurality of contacts on the major surface. The method further includes forming a plurality of trenches in the major surface of the substrate. The method also includes forming a plurality of openings in the wafer between the backside and the trenches in the major surface. The method further includes depositing an encapsulant on the backside of the wafer. At least some of the encapsulant passes through the openings in the wafer to at least partially fill the trenches in the major surface. The method also includes singulating the wafer to produce a plurality of chip scale packages having a major surface including one or more contacts and side walls at least partially covered with said encapsulant.

Abstract: The disclosure relates to a data transmission system (100) comprising a signal line (101) and a ground line (103). A first signal path (102) is provided between the signal line (101) and the ground line (103). The first signal path (102) comprises a Shockley diode (104) having a cathode (106) and an anode (108). The cathode (106) is connected to the ground line (103) and the anode (108) is connected to the signal line (101).

Abstract: A method of packing a semiconductor device is disclosed. The method includes placing a wafer on a carrier such that a backside of the wafer is facing up and a front side is facing down and non-permanently affixed to the surface of the carrier, performing lithography to mark area to be etched on the backside of the wafer, etching the marked areas from the backside of the wafer thus forming trenches that mark boundaries of individual devices on the wafer, applying a protective coating on the backside of the wafer thus filling the trenches and entire backside of the wafer with a protective compound and cutting the individual devices from the wafer.

Abstract: A semiconductor device and a method of making the same. The device includes a substrate comprising a major surface and a backside. The device also includes a dielectric partition for electrically isolating a first part of the substrate from a second part of the substrate. The dielectric partition extends through the substrate from the major surface to the backside.

Abstract: A method of making a plurality of semiconductor devices comprising a chip scale packages. The method includes providing a semiconductor wafer having a major surface and a backside. The method also includes forming a plurality of contacts on the major surface. The method further includes forming a plurality of trenches in the major surface of the substrate. The method also includes forming a plurality of openings in the wafer between the backside and the trenches in the major surface. The method further includes depositing an encapsulant on the backside of the wafer. At least some of the encapsulant passes through the openings in the wafer to at least partially fill the trenches in the major surface. The method also includes singulating the wafer to produce a plurality of chip scale packages having a major surface including one or more contacts and side walls at least partially covered with said encapsulant.

Abstract: Various embodiments relate to a light emitting diode protection circuit, including: a plurality of diodes connected in series; an input connected to a first diode of the plurality of diodes; an output; a first resistor connected between the plurality of diodes and the output; a transistor with a gate connected to a junction between the first resistor and the plurality of diodes and a source connected to the output; a second resistor connected between the input and drain of the transistor; and a silicon controlled rectifier (SCR) with an anode connected to the input, a base connected to the drain of the transistor, and a cathode connected to the output.

Abstract: The disclosure relates to a data transmission system (100) comprising a signal line (101) and a ground line (103). A first signal path (102) is provided between the signal line (101) and the ground line (103). The first signal path (102) comprises a Shockley diode (104) having a cathode (106) and an anode (108). The cathode (106) is connected to the ground line (103) and the anode (108) is connected to the signal line (101).

Abstract: A semiconductor device and a method of making the same. The device includes a semiconductor substrate provided in a chip-scale package (CSP). The device also includes a plurality of contacts provided on a major surface of the substrate. The device further includes an electrically floating metal layer forming an ohmic contact on a backside of the semiconductor substrate. The device is operable to conduct a current that passes through the substrate from a first of said plurality of contacts to a second of said plurality of contacts via the metal layer on the backside.

Abstract: A common mode choke comprising a first planar coil for receiving a first signal, a second planar coil for receiving a second signal, the first and second coils comprising substantially mirror images of one another and arranged side by side in a common plane, the first planar coil and second planar coil electromagnetically coupled by a closed coupling loop.

Abstract: A semiconductor device (300a) comprising: a substrate (302) having a first surface (303); an n-type well (304) extending from the first surface (303) into the substrate (302) and configured to form a depletion region (306) in the substrate (302) around the n-type well (304); an insulating layer (340) extending over the first surface (303) of the substrate (302) from the n-type well (304), the insulating layer (340) configured to form an inversion layer (342) in the substrate (302) extending from the n-type well (304) adjacent to the first surface (303); wherein a p-type floating channel stopper (370a) is provided, configured to extend through the inversion layer (342) to reduce electrical coupling between the n-type well (304) and at least part of the inversion layer (342), and is electrically disconnected from a remainder of the substrate (320) outside of the depletion region (306).

Abstract: The present disclosure relates to an electrostatic discharge (ESD) protection device. The electrostatic discharge protection device, may comprise: a semiconductor controlled rectifier; and a p-n diode. The semiconductor controlled rectifier and the diode may be integrally disposed laterally at a major surface of a semiconductor substrate; and a current path for the semiconductor controlled rectifier may be separate from a current path for the diode.

Abstract: An ESD protection circuit comprises a series connection of at least two protection components between a signal line to be protected and a return line (e.g. ground), comprising a first protection component connected to the signal line and a second protection component connected to the ground line. They are connected with opposite polarity so that when one conducts in forward direction the other conducts in reverse breakdown mode. A bias voltage source connects to the junction between the two protection components through a bias impedance. The use of the bias voltage enables the signal distortions resulting from the ESD protection circuit to be reduced.

Abstract: The present disclosure relates to an electrostatic discharge (ESD) protection device. The electrostatic discharge protection device, may comprise: a semiconductor controlled rectifier; and a p-n diode. The semiconductor controlled rectifier and the diode may be integrally disposed laterally at a major surface of a semiconductor substrate; and a current path for the semiconductor controlled rectifier may be separate from a current path for the diode.

Abstract: Circuit protection is provided. In accordance with one or more example embodiments, a thyristor-based circuit and a diode-based circuit are connected in series between an internal circuit terminal and reference terminal, for protecting the internal circuit terminal against circuit stresses such as overvoltage and/or overcurrent, as may be associated with electrostatic discharge. The thyristor and diode-based circuits operate in a first mode at which leakage current is limited by the thyristor, and in a second (protection) mode in which a voltage at the internal terminal exceeds a threshold level at which the thyristor-based circuit operates in a forward-biased mode and the diode operates in a breakdown mode, for shunting current between the internal circuit terminal and reference terminal.

Abstract: A semiconductor device (300a) comprising: a substrate (302) having a first surface (303); an n-type well (304) extending from the first surface (303) into the substrate (302) and configured to form a depletion region (306) in the substrate (302) around the n-type well (304); an insulating layer (340) extending over the first surface (303) of the substrate (302) from the n-type well (304), the insulating layer (340) configured to form an inversion layer (342) in the substrate (302) extending from the n-type well (304) adjacent to the first surface (303); wherein a p-type floating channel stopper (370a) is provided, configured to extend through the inversion layer (342) to reduce electrical coupling between the n-type well (304) and at least part of the inversion layer (342), and is electrically disconnected from a remainder of the substrate (320) outside of the depletion region (306).