Abstract: A method provided for interconnecting a buried wiring line and a source/drain body. The method includes: forming a fin structure on a substrate, the fin structure comprising at least one channel layer; forming a buried wiring line in a trench extending alongside the fin structure, wherein the buried wiring line is capped by a first insulating layer structure; forming a source/drain body on the at least one channel layer by epitaxy; forming a via hole in the first insulating layer structure to expose an upper surface of the buried wiring line; forming a metal via in the via hole; forming a second insulating layer structure over the first insulating layer structure, wherein a contact opening is defined in the second insulating layer structure to expose the source/drain body and an upper via portion of the metal via; and forming a source/drain contact in the contact opening, on the upper via portion and the source/drain body, thereby inter-connecting the buried wiring line and the source/drain body.

Abstract: In one aspect, a method of forming a semiconductor device including a plurality of stacked transistor devices having a bottom transistor device and a top transistor device can include: forming a plurality of parallel fin structures on a substrate; forming a sacrificial gate across the fin structures; forming bottom source/drain bodies for each bottom transistor device by epitaxy; forming a bottom dummy contact layer covering the bottom source/drain bodies; forming top source/drain bodies for each top transistor device over the bottom dummy contact layer by epitaxy; depositing an insulating material over the bottom dummy contact layer and the top source/drain bodies; replacing the sacrificial gate with a functional gate stack by a replacement metal gate process; patterning holes extending through the insulating material, with each hole exposing an upper surface portion of the bottom dummy contact layer; replacing the bottom dummy contact layer with one or more contact metals, which can include etching the dumm

Abstract: A method is provided for forming a semiconductor device.

Abstract: The disclosed method includes forming an initial layer stack comprising a sacrificial layer of a first semiconductor material and over the sacrificial layer a channel layer of a second semiconductor material, forming a fin structures by patterning trenches in the initial layer stack, forming an anchoring structure extending across the fin structures, and while the channel layers are anchored by the anchoring structure: removing the sacrificial layers by a selective etching of the first semiconductor material, thereby forming a longitudinal cavity underneath the channel layer of each fin structure, and depositing an insulating material to fill the cavities, wherein the insulating material is formed of a flowable dielectric, and subsequently recessing the at least one anchoring structure and the insulating material to a level below the cavities such that the insulating material remains in the cavities to form insulating layers underneath the channel layers of each fin structure.

Abstract: A method for forming a first transistor structure from a first channel layer and a second transistor structure from a second channel layer is disclosed. The first channel layer and the second channel layer are vertically stacked on a substrate. The method includes processing the first transistor structure from above, followed by processing the second transistor structure from the backside.

Abstract: According to an aspect of the present inventive concept there is provided a method for forming source/drain contacts, the method comprising: depositing a material layer over a first and second layer stack formed in a first and second device region of a substrate, respectively, each layer stack comprising a number of semiconductor channel layers and the layer stacks being separated by a trench filled with insulating material to form an insulating wall between the layer stacks and between the device regions; forming a contact partition trench in the material layer at a position above the insulating wall, and filling the contact partition trench with an insulating material to form a contact partition wall on top of the insulating wall; forming a first and a second source/drain contact trench on mutually opposite sides of the contact partition wall, the first source/drain contact trench being formed above a source/drain region in the first device region, and the second source/drain contact trench being formed

Abstract: A method for forming a semiconductor device is provided. The method comprises forming a device layer stack comprising an alternating sequence of lower sacrificial layers and channel layers, and a top sacrificial layer over the topmost channel layer, wherein the top sacrificial layer is thicker than each lower sacrificial layer; etching the top sacrificial layer to form a top sacrificial layer portion underneath the sacrificial gate structure; forming a first spacer on end surfaces of the top sacrificial layer portion; etching the channel and lower sacrificial layers while using the first spacer as an etch mask to form channel layer portions and lower sacrificial layer portions; etching the lower sacrificial layer portions to form recesses in the device layer stack, while the first spacer masks the end surfaces of the top sacrificial layer portion; and forming a second spacer in the recesses.

Abstract: Example embodiments relate to counteracting semiconductor material loss during semiconductor structure formation. One embodiment includes a method for forming a semiconductor structure. The method includes providing a structure. The structure includes a substrate. The structure also includes a layer stack on the substrate. The layer stack includes at least one semiconductor layer of a semiconductor material and at least one sacrificial layer under the semiconductor layer. Further, the structure includes a trench through the layer stack. The further also includes forming a recess in the layer stack by etching a portion of the sacrificial layer exposed by the trench. The etching includes a preferential etch of the sacrificial layer with respect to the semiconductor layer. Additionally, the method includes epitaxially growing a liner of the semiconductor material onto surfaces of the semiconductor layer exposed by the trench.

Abstract: A method of forming aligned gates for horizontal nanowires or nanosheets, comprising: providing a wafer which comprises at least one fin of sacrificial layers alternated with functional layers, and a dummy gate covering a section of the fin between a first end and a second end; at least partly removing the sacrificial layers at the first end and the second end thereby forming a void between the functional layers at the first and end such that the void is partly covered by the dummy gate; providing resist material which oxidizes upon EUV exposure; exposing the wafer to EUV light; selectively removing the dummy gate and the unexposed resist; forming a gate between the functional layers and between the exposed resist at the first end and at the second end.

Abstract: A method of forming aligned gates for horizontal nanowires or nanosheets, comprising: providing a wafer which comprises at least one fin of sacrificial layers alternated with functional layers, and a dummy gate covering a section of the fin between a first end and a second end; at least partly removing the sacrificial layers at the first end and the second end thereby forming a void between the functional layers at the first and end such that the void is partly covered by the dummy gate; providing resist material which oxidizes upon EUV exposure; exposing the wafer to EUV light; selectively removing the dummy gate and the unexposed resist; forming a gate between the functional layers and between the exposed resist at the first end and at the second end.

Abstract: The present disclosure relates to a method of forming a semiconductor device comprising horizontal nanowires. The method comprises depositing a multilayer stack on a substrate, the multilayer stack comprising first sacrificial layers alternated with layers of nanowire material; forming at least one fin in the multilayer stack; applying an additional sacrificial layer around the fin such that a resulting sacrificial layer is formed all around the nanowire material; and forming a nanowire spacer, starting from the resulting sacrificial layer, around the nanowire material at an extremity of the nanowire material. The present disclosure also relates to a corresponding semiconductor device.

Abstract: A method of forming an internal spacer between nanowires, the method involving: providing a fin comprising a stack of layers of sacrificial material alternated with nanowire material, and selectively removing part of the sacrificial material, thereby forming a recess. The method also involves depositing dielectric material into the recess resulting in dielectric material within the recess and excess dielectric material outside the recess, where a crevice remains in the dielectric material in each recess, and removing the excess dielectric material using a first etchant. The method also involves enlarging the crevices to form a gap using a second etchant such that a remaining dielectric material still covers the sacrificial material and partly covers the nanowire material, and such that outer ends of the nanowire material are accessible; and growing electrode material on the outer ends such that the electrode material from neighboring outer ends merge, thereby covering the gap.

Abstract: The present disclosure relates to a method of forming an internal spacer between nanowires in a semiconductor device. The method includes providing a semiconductor structure comprising at least one fin. The at least one fin is comprised of a stack of layers of sacrificial material alternated with layers of nanowire material. The semiconductor structure is comprised of a dummy gate which partly covers the stack of layers of the at least one fin. The method also includes removing at least the sacrificial material next to the dummy gate and oxidizing the sacrificial material and the nanowire material next to the dummy gate. This removal results, respectively, in a spacer oxide and in a nanowire oxide. Additionally, the method includes removing the nanowire oxide until at least a part of the spacer oxide is remaining, wherein the remaining spacer oxide is the internal spacer.

Abstract: A method of forming an internal spacer between nanowires, the method involving: providing a fin comprising a stack of layers of sacrificial material alternated with nanowire material, and selectively removing part of the sacrificial material, thereby forming a recess. The method also involves depositing dielectric material into the recess resulting in dielectric material within the recess and excess dielectric material outside the recess, where a crevice remains in the dielectric material in each recess, and removing the excess dielectric material using a first etchant. The method also involves enlarging the crevices to form a gap using a second etchant such that a remaining dielectric material still covers the sacrificial material and partly covers the nanowire material, and such that outer ends of the nanowire material are accessible; and growing electrode material on the outer ends such that the electrode material from neighboring outer ends merge, thereby covering the gap.

Abstract: The present disclosure relates to a method of forming a semiconductor device comprising horizontal nanowires. The method comprises depositing a multilayer stack on a substrate, the multilayer stack comprising first sacrificial layers alternated with layers of nanowire material; forming at least one fin in the multilayer stack; applying an additional sacrificial layer around the fin such that a resulting sacrificial layer is formed all around the nanowire material; and forming a nanowire spacer, starting from the resulting sacrificial layer, around the nanowire material at an extremity of the nanowire material. The present disclosure also relates to a corresponding semiconductor device.

Abstract: The present disclosure relates to a method of forming an internal spacer between nanowires in a semiconductor device. The method includes providing a semiconductor structure comprising at least one fin. The at least one fin is comprised of a stack of layers of sacrificial material alternated with layers of nanowire material. The semiconductor structure is comprised of a dummy gate which partly covers the stack of layers of the at least one fin. The method also includes removing at least the sacrificial material next to the dummy gate and oxidizing the sacrificial material and the nanowire material next to the dummy gate. This removal results, respectively, in a spacer oxide and in a nanowire oxide. Additionally, the method includes removing the nanowire oxide until at least a part of the spacer oxide is remaining, wherein the remaining spacer oxide is the internal spacer.

Abstract: Disclosed is a method of manufacturing an integrated circuit comprising a bipolar transistor, the method comprising providing a substrate (10) comprising a pair of first isolation regions (12) separated from each other by an active region (11) comprising a collector impurity said bipolar transistor; forming a base layer stack (14, 14?) over said substrate; forming a further stack of a migration layer (15) having a first migration temperature and an etch stop layer (20) over said base layer stack (14); forming a base contact layer (16) having a second migration temperature over the further stack, the second migration temperature being higher than the first migration temperature; etching an emitter window (28) in the base contact layer over the active region, said etching step terminating at the etch stop layer; at least partially removing the etch stop layer, thereby forming cavities (29) extending from the emitter window in between the base contact layer and the redistribution layer; and exposing the resultan

Abstract: Methods and systems for processing a silicon wafer are disclosed. A method includes providing a flash memory region in the silicon wafer and providing a bipolar transistor with a polysilicon external base in the silicon wafer. The flash memory region and the bipolar transistor are formed by depositing a single polysilicon layer common to both the flash memory region and the bipolar transistor.

Abstract: Consistent with an example embodiment, there is method of manufacturing a bipolar transistor comprising providing a substrate including an active region; depositing a layer stack; forming a base window over the active region in said layer stack; forming at least one pillar in the base window, wherein a part of the pillar is resistant to polishing; depositing an emitter material over the resultant structure, thereby filling said base window; and planarizing the deposited emitter material by polishing. Consistent with another example embodiment, a bipolar transistor may be manufactured according to the afore-mentioned method.

Abstract: A tunnel field effect transistor and a method of making the same. The transistor includes a semiconductor substrate. The transistor also includes a gate located on a major surface of the substrate. The transistor further includes a drain of a first conductivity type. The transistor also includes a source of a second conductivity type extending beneath the gate. The source is separated from the gate by a channel region and a gate dielectric. The transistor is operable to allow charge carrier tunnelling from an inversion layer through an upper surface of the source.