Abstract: A CMOS low frequency oscillator circuit comprising an amplifier (10) and an interface for connecting a first and a second terminal of an external crystal oscillator (14) in a feedback path of the amplifier (10). In one aspect, the oscillator circuit further comprises a regulated current source (24) supplying a regulated current to the amplifier (10) controlled by the voltage swing across the external crystal oscillator (14); and a constant current source (32) supplying a minimum constant current to the amplifier (10) independent of the voltage swing across the external crystal oscillator (14).

Abstract: Circuit arrangement for checking memory cells of programmable MOS-integrated semiconductor memories, especially non-volatile semiconductor memories of the floating-gate type, has an active programming and read mode of operation wherein all word lines of the semiconductor memory with the exception of one selected word line are at a low level. The circuit arrangement also has an inactive power-down mode of operation, wherein all word lines at a high level. Both of the modes of operation are represented by a signal having a first level for the active mode of operation and a second level for the inactive mode of operation.

Abstract: Circuit arrangement for a read-only memory organized in rows and columns, including bit lines having potentials applied thereto, and selection circuits being connected to the bit lines, being addressed by a bit line decoder and containing at least one selection transistor having a cut-off voltage and a gate potential, for preventing bit line potentials from dropping below a given value at which the selection circuits become conducting without having been selected by the bit line decoder, including current-feed lines each being connected to a different one of the bit lines for feeding current to the bit lines and for ensuring that for each of the selection circuits not selected by the bit line decoder the difference between at least one gate potential of the participating selection transistors and the respective bit line potential is smaller than the cut-off voltage of the respective selection transistors.