Abstract: An apparatus is provided for mounting a Very Large Scale Integration (VLSI) chip such as a microprocessor on the back plane of a computer chassis. In one embodiment, the mounting on the computer chassis is configured to provide a current supply connection for delivering a high level of current to the microprocessor from a current source through the computer chassis. Also provided are an apparatus for mounting a VLSI chip such as a microprocessor on the chassis of a computer system in order to dissipate heat from the VLSI chip to the ambient outside the computer system through the computer chassis. Also provided are an apparatus for signal interconnections among one or several VLSI chips such as microprocessors mounted on the chassis of a computer to provide signal capacity with strong integrity. Also provided are an apparatus for mounting a power supply for a VLSI chip package on the back chassis of a computer.

Abstract: A method and apparatus are provided for mounting a Very Large Scale Integration (VLSI) chip such as a microprocessor on the back plane of a computer chassis. In one embodiment, the mounting on the computer chassis is configured to provide a current supply connection for delivering a high level of current to the microprocessor from a current source through the computer chassis. Also provided are a method and apparatus for mounting a VLSI chip such as a microprocessor on the chassis of a computer system in order to dissipate heat from the VLSI chip to the ambient outside the computer system through the computer chassis. Also provided are a method and apparatus for signal interconnections among one or several VLSI chips such as microprocessors mounted on the chassis of a computer to provide signal capacity with strong integrity. Also provided are a method and apparatus for mounting a power supply for a VLSI chip package on the back chassis of a computer.

Abstract: A method and apparatus for dynamically predicting the outcome and the tar address of a multiple-target branch instruction, where the multiple-target branch instruction contains at least two potential target addresses, not including the fall through address. In addition, this method and apparatus can also be used to predict multiple single-target branches simultaneously. The apparatus stores information indicating the outcome of previous executions and predictions of the multiple-target branch instruction in a branch prediction table. In addition, multiple target addresses (at least two) are associated with the multiple-target branch instruction. Using the information indicating the outcome of the previous execution of the multiple-target branch instruction, the apparatus predicts the outcome of a next execution of the multiple-target branch instruction, and predicts which, if any, of the target addresses associated with the multiple-target branch instruction, will be taken.

Abstract: A technique for providing adaptive 128-bit load and store operations to support architecture extensions for computations on a 128-bit quadruple precision format, in which a single set of load and store instructions provides for save and restore operations on both 80-bit and 128-bit floating point register files. A 128-bit load and store instructions are utilized for moving values that are 128-bit aligned in memory. The transfer entails the movement of data between a 128-bit memory boundary and a floating point register file for register save and restore operations. In one embodiment, 80-bit registers are used and in a second embodiment 128-bit registers are used. The same instructions operate on both the 80-bit and 128-bit registers to map the content of a given register into a 128-bit boundary field in memory. A load/store unit allocates the bit positioning so that when 80-bit registers are used, the 80 bits are moved into the most significant bit positions of the 128-bit boundary field.

Abstract: A processor and method that reduces instruction fetch penalty in the execution of a program sequence of instructions comprises a branch predict instruction that is inserted into the program at a location which precedes the branch. The branch predict instruction has an opcode that specifies a branch as likely to be taken or not taken, and which also specifies a target address of the branch. A block of target instructions, starting at the target address, is prefetched into the instruction cache of the processor so that the instructions are available for execution prior to the point in the program where the branch is encountered. Also specified by the opcode is an indication of the size of the block of target instructions, and a trace vector of a path in the program sequence that leads to the target from the branch predict instruction for better utilization of limited memory bandwidth.

Abstract: A technique for providing adaptive 128-bit load and store operations to support architecture extensions for computations on a 128-bit quadruple precision format, in which a single set of load and store instructions provides for save and restore operations on both 80-bit and 128-bit floating point register files. A 128-bit load and store instructions are utilized for moving values that are 128-bit aligned in memory. The transfer entails the movement of data between a 128-bit memory boundary and a floating point register file for register save and restore operations. In one embodiment, 80-bit registers are used and in a second embodiment 128-bit registers are used. The same instructions operate on both the 80-bit and 128-bit registers to map the content of a given register into a 128-bit boundary field in memory. A load/store unit allocates the bit positioning so that when 80-bit registers are used, the 80 bits are moved into the most significant bit positions of the 128-bit boundary field.