Abstract: An hardware emulation environment is disclosed wherein software execution is accelerated by switching memory and/or peripheral and clock implementation from the hardware emulator toga faster running processor board coupled to the hardware emulator. A switch is positioned between the hardware emulator and a processor running on the processor board. A design block implemented on a dedicated resource, such as memory or a peripheral, is located on the processor board and is designed to functionally mimic a design block modelled in programmable resources in the hardware emulator. In one embodiment, a user selectively configures a switch to accelerate the software execution by choosing a trigger event, such as a memory range or a software breakpoint. Upon detecting the trigger event, the switch switches the clock and/or bus routing so that the processor communicates directly with the design block on the processor board, rather than with a functionally equivalent design block in the hardware emulator.

Abstract: According to the invention, an IP core is clocked during a debugging operation by switching from the clock used for testing the device under test to a clock oscillator or any other free-running clock source.