Patents by Inventor Hans Norstroem

Hans Norstroem has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7618865
    Abstract: A method in the fabrication of a monolithically integrated vertical device on an SOI substrate comprises the steps of providing an SOI substrate including, from bottom to top, a silicon bulk material, an insulating layer, and an monocrystalline silicon layer; forming an opening in the substrate, which extends into the bulk-material, forming silicon oxide on exposed silicon surfaces in the opening and subsequently removing the formed oxide, whereby steps in the opening are formed; forming a region of epitaxial silicon in the opening; and forming a deep trench in an area around the opening, whereby the steps in the opening are removed.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: November 17, 2009
    Assignee: Infineon Technologies AG
    Inventors: Ted Johansson, Hans Norstroem
  • Patent number: 7456069
    Abstract: A method in the fabrication of an I2L circuit comprises (i) forming a common base of a lateral bipolar transistor and emitter of a vertical bipolar multicollector transistor, a common collector of the lateral transistor and base of the vertical multicollector transistor, and an emitter of the lateral transistor in a substrate; (ii) forming, from a first deposited polycrystalline layer, a contact region for the common collector/base and a contact region for the emitter of the lateral transistor; (iii) forming an isolation structure for electric isolation of the polycrystalline contact region for the common collector/base; and (iv) forming, from a second deposited polycrystalline layer, a contact region for the common base/emitter and multiple collectors of the vertical multicollector transistor.
    Type: Grant
    Filed: October 6, 2005
    Date of Patent: November 25, 2008
    Assignee: Infineon Technologies AG
    Inventors: Ted Johansson, Hans Norstroem
  • Publication number: 20070048928
    Abstract: A method in the fabrication of a monolithically integrated vertical device on an SOI substrate comprises the steps of providing an SOI substrate including, from bottom to top, a silicon bulk material, an insulating layer, and an monocrystalline silicon layer; forming an opening in the substrate, which extends into the bulk-material, forming silicon oxide on exposed silicon surfaces in the opening and subsequently removing the formed oxide, whereby steps in the opening are formed; forming a region of epitaxial silicon in the opening; and forming a deep trench in an area around the opening, whereby the steps in the opening are removed.
    Type: Application
    Filed: August 31, 2005
    Publication date: March 1, 2007
    Applicant: Infineon Technologies AG
    Inventors: Ted Johansson, Hans Norstroem
  • Publication number: 20060105517
    Abstract: A method in the fabrication of an I2L circuit comprises (i) forming a common base of a lateral bipolar transistor and emitter of a vertical bipolar multicollector transistor, a common collector of the lateral transistor and base of the vertical multicollector transistor, and an emitter of the lateral transistor in a substrate; (ii) forming, from a first deposited polycrystalline layer, a contact region for the common collector/base and a contact region for the emitter of the lateral transistor; (iii) forming an isolation structure for electric isolation of the polycrystalline contact region for the common collector/base; and (iv) forming, from a second deposited polycrystalline layer, a contact region for the common base/emitter and multiple collectors of the vertical multicollector transistor.
    Type: Application
    Filed: October 6, 2005
    Publication date: May 18, 2006
    Applicant: Infineon Technologies AG
    Inventors: Ted Johansson, Hans Norstroem
  • Publication number: 20060076645
    Abstract: A method for producing vertical bipolar transistors having different voltage breakdown and high-frequency performance characteristics on a single die comprises forming, for each of the vertical bipolar transistors, a buried collector region, and base and emitter regions above the buried collector region. The lateral extensions and locations of the base and emitter regions and of the buried collector region are, for each of the vertical bipolar transistors, selected to create an overlap between the base and emitter regions, and the buried collector region, as seen from above, wherein at least some of the overlaps are selected to be different.
    Type: Application
    Filed: September 30, 2005
    Publication date: April 13, 2006
    Applicant: Infineon Technologies AG
    Inventors: Patrick Algotsson, Hans Norstroem, Karin Andersson