Abstract: A circuit which responds to the application of a pulse to its input (6) by generating a pulse at its output (3), the output pulse having a minimum duration T and being extended by the remaining length of the input pulse should the input pulse be still present at the end of the time T, comprises a pair of semiconductor switches (1,2) connecting the output (3) to points (5,4) carrying respective logic levels. The input pulse closes the first switch (1) and also inhibits a gate circuit (9). The resulting logic level on the output (3) closes the second switch (2) after delay by T in a delay circuit (13) and transmission through the gate circuit (9), thereby restoring the original logic level. The instant when this occurs coincides with the presence of the delayed output pulse at the output (14) of the delay circuit and the absence of the pulse at the arrangement input (6). A hold circuit circuit (15) may be provided for holding the logic level currently present at the output (3).

Abstract: An addressable memory unit has address input buffer circuits which output a pair of output connections on which, in read or write mode, two signals which are complementary to one another are present but which may also adopt equal values in such a manner as to cause a predecoder and line selector to select all or none of the selection lines controlling the cells of the memory accessed.

Abstract: When using a laser programmable fuse, a circuit should be 100% stable both before and after the fuse is blown. So far no CMOS circuit can be 100% stable without drawing a constant current. With the "Master fuse Enable" scheme one fuse circuit (master fuse) draws current while disabling all other fuse circuits on-chip. Thus giving 100% stability and reducing power consumption on a chip where no fusing has been done. If, however, one wished to use the rest of the fuses, then the master fuse is blown and all fuse circuits now become active and draw current.

Abstract: An integrated circuit having logic circuits and a logic output buffer, which circuit includes the following sub-circuits: a memory circuit and a logic output circuit, in which no tri-state occurs at the output during a sequence of data signals at the input, wherein the drive of the circuit by means of control signals is not critical over time because the first data signal from the sequence switches off the tri-state mode, the tri-state mode again being introduced if a control signal is furnished, and in the absence of this control signal, the last data signal is retained.

Abstract: A static RAM memory is optimized for speed. The memory is divided into major memory matrices and each major memory matrix is divided into memory blocks. The memory blocks are divided in groups that per group have address bits in common, which however are per group coupled to separate pads or sets of pads. These pads are interconnected on the package to common package pins.

Abstract: An integrated matrix memory includes standard sub-blocks and a redundant block. Each of the standard sub-blocks has a fixed number of standard sub-blocks, and the redundant block has one or more redundant sub-blocks. For addressing there is provided a detector for the address of a faulty standard sub-block. In that case a redundant sub-block is selected. Selection is realized by way of a sub-bus which forms part of the data path. Thus, a redundant system is achieved in which delay is minimized.

Abstract: Random access memory unit having a plurality of test modes, which is constructed as an integrated circuit and which does not include specific input/output pins to define and to command the passage to test mode. This unit is equipped with means (1) for detecting whether a predefined sequence of logic signals, which is not contained, within a set of sequences which are normally used, but the voltages of which are nevertheless included within the range of voltages which are specified for such signals, is supplied to certain inputs (CE, WE, AO), and for placing the unit in-test mode when such a sequence has been detected. In order to define the nature of the test to be performed, address input terminals, (A1-A8) of the unit are connected to a test mode decoding circuit (2), in which the data applied to the said input terminals are used as data defining the nature of the test to be performed.

Abstract: Data are frequently transmitted via a dual bus line by means of differential signals which are evaluated by a differential amplifier, particularly for reasons of protection against interference. However, such a differential amplifier only has a limited input voltage range, or a dead voltage range of the input signals within which it is not capable of operating. To prevent the voltages on both bus lines from getting into this dead voltage range, either due to a common-mode interference signal on the bus lines or due to a voltage dip in the feed voltage of the differential amplifier, the two bus lines are connected in accordance with the invention to an adjusting circuit which changes the voltages of both bus lines by the same amount in the direction out of the dead voltage range. This prevents unspecified conditions of the differential amplifier without significantly influencing the differential signal on the two bus lines. The application for an integrated memory is described.

Abstract: A push-pull output circuit which is powered by a 5-V supply voltage and in which the "push" part comprises a PMOS transistor and the "pull" comprises a PMOS transistor and an NMOS transistor. The NMOS transistor is driven via a detection circuit so that no hot carrier stress occurs in the NMOS transistor.