Abstract: A generator circuit in an integrated semiconductor circuit for generating a clock voltage having a voltage being raised with respect to a supply potential of the generator circuit includes a first CMOS inverter having an input connected to a first clock signal and having an output carrying a clock voltage as an output signal of the generator circuit. A second CMOS inverter has an input connected to a second clock signal and has an output. The inverters have transistors of a first conduction type with source terminals. A transfer transistor of the first conduction type is connected between the source terminals and a supply potential. A capacitor is connected between the source terminals and a pump signal. The transfer transistor has a gate terminal connected to the output of the second CMOS inverter.

Abstract: An integrated semiconductor memory includes n identical memory cell fields, n.m data lines for writing memory data into and reading memory data out of the fields, m data input terminals receiving the memory data to be written into the semiconductor memory during writing, m first data switches for applying the memory data to a respective one of the n data lines as a function of addressing data, m second data switches each selecting a respective one of the n data lines when reading out the memory data applied to the n data lines as a function of the addressing data, an evaluation circuit connected to n of the n.

Abstract: A decoding circuit for decoding information represented by input signals includes: sources of transistors of one channel type in each of four CMOS inverters connected to a first supply potential; sources of transistors of another channel type in each two inverters connected to each other and to one or the other of first connecting points; two first switching transistors of the other channel type each having a drain connected to a first connecting point and a source connected to each other and to a last connecting point; the gates of each of the two first switching transistors being connected to a second input signal or a signal complementary thereto of four further input signals complementary to each other in pairs; a last switching transistor of the other channel type having a drain connected to the last connecting point, a source connected to a second supply potential and a gate connected to an input for an individual input signal; the gates of both transistors of two of the inverters being connected to a f