Abstract: In a signal processor computing arrangement comprising an ALU (11) and a multiplier (21), two selectively usable accumulators (37, 41) and gating circuitry (61, 63) are provided to allow alternating computation and accumulation of product terms for two output values with sets of input values that overlap. This saves memory accesses by using the same operand twice for different output values, and requires only one processor cycle per partial term and output value. A specific pipeline multiplier (21) is provided consisting of two partial sections (29, 31) with an intermediate pipeline register (33) to allow applying a second set of input operands while computation of the product of a first set of operands is still in progress.