Patents by Inventor Hans-Peter Felsl

Hans-Peter Felsl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11018252
    Abstract: A power semiconductor transistor includes a semiconductor body having a front side and a backside with a backside surface. The semiconductor body includes a drift region of a first conductivity type and a field stop region of the first conductivity type. The field stop region is arranged between the drift region and the backside and includes, in a cross-section along a vertical direction from the backside to the front side, a concentration profile of donors of the first conductivity type that has: a first local maximum at a first distance from the backside surface, a front width at half maximum associated with the first local maximum, and a back width at half maximum associated with the first local maximum. The front width at half maximum is smaller than the back width at half maximum and amounts to at least 8% of the first distance.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: May 25, 2021
    Assignee: Infineon Technologies AG
    Inventors: Hans Peter Felsl, Moriz Jelinek, Volodymyr Komarnitskyy, Konrad Schraml, Hans-Joachim Schulze
  • Publication number: 20200098911
    Abstract: A power semiconductor transistor includes a semiconductor body having a front side and a backside with a backside surface. The semiconductor body includes a drift region of a first conductivity type and a field stop region of the first conductivity type. The field stop region is arranged between the drift region and the backside and includes, in a cross-section along a vertical direction from the backside to the front side, a concentration profile of donors of the first conductivity type that has: a first local maximum at a first distance from the backside surface, a front width at half maximum associated with the first local maximum, and a back width at half maximum associated with the first local maximum. The front width at half maximum is smaller than the back width at half maximum and amounts to at least 8% of the first distance.
    Type: Application
    Filed: September 23, 2019
    Publication date: March 26, 2020
    Inventors: Hans Peter Felsl, Moriz Jelinek, Volodymyr Komarnitskyy, Konrad Schraml, Hans-Joachim Schulze
  • Patent number: 9741795
    Abstract: An IGBT includes at least one first type transistor cell, including a base region, first and second emitter regions, and a body region arranged between the first emitter region and base region. The base region is arranged between the body region and second emitter region. A gate electrode adjacent the body region is dielectrically insulated from the body region by a gate dielectric. A base electrode adjacent the base region is dielectrically insulated from the base region by a base electrode dielectric. The base region has a first base region section adjoining the base electrode dielectric and a second base region section arranged between the second emitter region and the first base region section. A ratio between the doping concentration of the first base region section and the doping concentration of the second base region section is at least 10. The base electrode dielectric is thicker than the gate dielectric.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: August 22, 2017
    Assignee: Infineon Technologies AG
    Inventors: Christian Philipp Sandow, Hans-Joachim Schulze, Johannes Georg Laven, Franz-Josef Niedernostheide, Frank Pfirsch, Hans-Peter Felsl
  • Patent number: 9412854
    Abstract: An IGBT module is provided. The IGBT module has at least a first individual IGBT with a first softness during switching-off the IGBT module, and at least a second individual IGBT connected in parallel to the at least one first IGBT. The at least one second individual IGBT has a second softness during switching-off the IGBT module which is different than the first softness. Further a circuit and an electronic power device having two individual IGBTs, which are connected in parallel, are provided.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: August 9, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans-Peter Felsl, Hans-Joachim Schulze, Franz-Josef Niedernostheide, Thomas Raker
  • Patent number: 9385181
    Abstract: A semiconductor diode includes a semiconductor body having opposite first and second sides. A first and a second semiconductor region are consecutively arranged along a lateral direction at the second side. The first and second semiconductor regions are of opposite first and second conductivity types and are electrically coupled to an electrode at the second side. The semiconductor diode further includes a third semiconductor region of the second conductivity type buried in the semiconductor body at a distance from the second side. The second and third semiconductor regions are separated from each other.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: July 5, 2016
    Assignee: Infineon Technologies AG
    Inventors: Hans Peter Felsl, Elmar Falck, Manfred Pfaffenlehner, Frank Hille, Andreas Haertl, Holger Schulze, Daniel Schloegl
  • Patent number: 9349829
    Abstract: A method of manufacturing a transistor device includes forming a semiconductor heterostructure including a plurality of alternating two-dimensional electron gasses (2DEGs) and two-dimensional hole gasses (2DHGs) extending in parallel at different depths in the semiconductor heterostructure, the 2DEGs forming current channels of the transistor device, forming a source extending into the semiconductor heterostructure in contact with the 2DEGs at a first end of the current channels, forming a drain extending into the semiconductor heterostructure in contact with the 2DEGs at an opposing second end of the current channels, and forming a plurality of spaced apart gate structures extending into the semiconductor heterostructure and including an electrically conductive material separated from the surrounding semiconductor heterostructure by an insulating material.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: May 24, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Clemens Ostermaier, Gerhard Prechtl, Oliver Haeberlen, Hans Peter Felsl
  • Patent number: 9293524
    Abstract: A semiconductor device has a semiconductor body with bottom and top sides and a lateral surface. An active semiconductor region is formed in the semiconductor body and an edge region surrounds the active semiconductor region. A first semiconductor zone of a first conduction type is formed in the edge region. An edge termination structure having at least N field limiting structures is formed in the edge region. Each of the field limiting structures has a field ring and a separation trench formed in the semiconductor body, where N is at least 1. Each of the field rings has a second conduction type, forms a pn-junction with the first semiconductor zone and surrounds the active semiconductor region. For each of the field limiting structures, the separation trench of that field limiting structure is arranged between the field ring of that field limiting structure and the active semiconductor region.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: March 22, 2016
    Assignee: Infineon Technologies AG
    Inventors: Elmar Falck, Wolfgang Roesener, Hans Peter Felsl, Andre Stegner
  • Publication number: 20160005818
    Abstract: An IGBT includes at least one first type transistor cell, including a base region, first and second emitter regions, and a body region arranged between the first emitter region and base region. The base region is arranged between the body region and second emitter region. A gate electrode adjacent the body region is dielectrically insulated from the body region by a gate dielectric. A base electrode adjacent the base region is dielectrically insulated from the base region by a base electrode dielectric. The base region has a first base region section adjoining the base electrode dielectric and a second base region section arranged between the second emitter region and the first base region section. A ratio between the doping concentration of the first base region section and the doping concentration of the second base region section is at least 10. The base electrode dielectric is thicker than the gate dielectric.
    Type: Application
    Filed: September 15, 2015
    Publication date: January 7, 2016
    Inventors: Christian Philipp Sandow, Hans-Joachim Schulze, Johannes Georg Laven, Franz-Josef Niedernostheide, Frank Pfirsch, Hans-Peter Felsl
  • Publication number: 20150318347
    Abstract: A semiconductor device has a semiconductor body with bottom and top sides and a lateral surface. An active semiconductor region is formed in the semiconductor body and an edge region surrounds the active semiconductor region. A first semiconductor zone of a first conduction type is formed in the edge region. An edge termination structure having at least N field limiting structures is formed in the edge region. Each of the field limiting structures has a field ring and a separation trench formed in the semiconductor body, where N is at least 1. Each of the field rings has a second conduction type, forms a pn-junction with the first semiconductor zone and surrounds the active semiconductor region. For each of the field limiting structures, the separation trench of that field limiting structure is arranged between the field ring of that field limiting structure and the active semiconductor region.
    Type: Application
    Filed: May 2, 2014
    Publication date: November 5, 2015
    Inventors: Elmar Falck, Wolfgang Roesner, Hans Peter Felsl, Andre Stegner
  • Patent number: 9166027
    Abstract: An IGBT includes at least one first type transistor cell, including a base region, a first emitter region, a body region, and a second emitter region. The body region is arranged between the first emitter region and the base region. The base region is arranged between the body region and the second emitter region. The IGBT further includes a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric, and a base electrode adjacent the base region and dielectrically insulated from the base region by a base electrode dielectric. The base region has a first base region section adjoining the base electrode dielectric and a second base region section arranged between the second emitter region and the first base region section. A doping concentration of the first base region section is higher than a doping concentration of the second base region section.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: October 20, 2015
    Assignee: Infineon Technologies AG
    Inventors: Christian Philipp Sandow, Hans-Joachim Schulze, Johannes Georg Laven, Franz-Josef Niedernostheide, Frank Pfirsch, Hans-Peter Felsl
  • Patent number: 9105682
    Abstract: Disclosed is a semiconductor component that includes a semiconductor body, a first emitter region of a first conductivity type in the semiconductor body, a second emitter region of a second conductivity type spaced apart from the first emitter region in a vertical direction of the semiconductor body, a base region of one conductivity type arranged between the first emitter region and the second emitter region, and at least two higher doped regions of the same conductivity type as the base region and arranged in the base region. The at least two higher doped regions are spaced apart from one another in a lateral direction of the semiconductor body and separated from one another only by sections of the base region.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: August 11, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans-Peter Felsl, Thomas Raker, Hans-Joachim Schulze, Franz-Josef Niedernostheide
  • Publication number: 20150221748
    Abstract: A method of manufacturing a transistor device includes forming a semiconductor heterostructure including a plurality of alternating two-dimensional electron gasses (2DEGs) and two-dimensional hole gasses (2DHGs) extending in parallel at different depths in the semiconductor heterostructure, the 2DEGs forming current channels of the transistor device, forming a source extending into the semiconductor heterostructure in contact with the 2DEGs at a first end of the current channels, forming a drain extending into the semiconductor heterostructure in contact with the 2DEGs at an opposing second end of the current channels, and forming a plurality of spaced apart gate structures extending into the semiconductor heterostructure and including an electrically conductive material separated from the surrounding semiconductor heterostructure by an insulating material.
    Type: Application
    Filed: April 17, 2015
    Publication date: August 6, 2015
    Inventors: Clemens Ostermaier, Gerhard Prechtl, Oliver Haeberlen, Hans Peter Felsl
  • Publication number: 20150206983
    Abstract: A semiconductor diode includes a semiconductor body having opposite first and second sides. A first and a second semiconductor region are consecutively arranged along a lateral direction at the second side. The first and second semiconductor regions are of opposite first and second conductivity types and are electrically coupled to an electrode at the second side. The semiconductor diode further includes a third semiconductor region of the second conductivity type buried in the semiconductor body at a distance from the second side. The second and third semiconductor regions are separated from each other.
    Type: Application
    Filed: January 23, 2014
    Publication date: July 23, 2015
    Inventors: Hans Peter Felsl, Elmar Falck, Manfred Pfaffenlehner, Frank Hille, Andreas Haertl, Holger Schulze, Daniel Schloegl
  • Patent number: 9048095
    Abstract: A method of manufacturing a semiconductor device includes forming a semiconductor diode by forming a drift region, forming a first semiconductor region of a first conductivity type in or on the drift region and electrically coupling the first semiconductor region to a first terminal via a first surface of a semiconductor body, etching a trench into the semiconductor body, and forming a channel region of a second conductivity type in the trench and electrically coupling the channel region to the first terminal via the first surface of the semiconductor body. A first side of the channel region adjoins the first semiconductor region.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: June 2, 2015
    Assignee: Infineon Technologies AG
    Inventors: Anton Mauder, Franz Hirler, Hans Peter Felsl, Hans-Joachim Schulze
  • Patent number: 9035355
    Abstract: A transistor device includes a semiconductor heterostructure including a plurality of alternating two-dimensional electron gasses (2DEGs) and two-dimensional hole gasses (2DHGs) extending in parallel at different depths in the semiconductor heterostructure. The 2DEGs form current channels of the transistor device. The transistor device further includes a source extending into the semiconductor heterostructure in contact with the 2DEGs at a first end of the current channels, and a drain extending into the semiconductor heterostructure in contact with the 2DEGs at an opposing second end of the current channels. The transistor device also includes a plurality of spaced apart gate structures extending into the semiconductor heterostructure and including an electrically conductive material separated from the surrounding semiconductor heterostructure by an insulating material.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: May 19, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Clemens Ostermaier, Gerhard Prechtl, Oliver Haeberlen, Hans Peter Felsl
  • Publication number: 20150091053
    Abstract: An IGBT includes at least one first type transistor cell, including a base region, a first emitter region, a body region, and a second emitter region. The body region is arranged between the first emitter region and the base region. The base region is arranged between the body region and the second emitter region. The IGBT further includes a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric, and a base electrode adjacent the base region and dielectrically insulated from the base region by a base electrode dielectric. The base region has a first base region section adjoining the base electrode dielectric and a second base region section arranged between the second emitter region and the first base region section. A doping concentration of the first base region section is higher than a doping concentration of the second base region section.
    Type: Application
    Filed: September 30, 2013
    Publication date: April 2, 2015
    Inventors: Christian Philipp Sandow, Hans-Joachim Schulze, Johannes Georg Laven, Franz-Josef Niedernostheide, Frank Pfirsch, Hans-Peter Felsl
  • Publication number: 20140370693
    Abstract: A method of manufacturing a semiconductor device includes forming a semiconductor diode by forming a drift region, forming a first semiconductor region of a first conductivity type in or on the drift region and electrically coupling the first semiconductor region to a first terminal via a first surface of a semiconductor body, etching a trench into the semiconductor body, and forming a channel region of a second conductivity type in the trench and electrically coupling the channel region to the first terminal via the first surface of the semiconductor body. A first side of the channel region adjoins the first semiconductor region.
    Type: Application
    Filed: August 28, 2014
    Publication date: December 18, 2014
    Inventors: Anton Mauder, Franz Hirler, Hans Peter Felsl, Hans-Joachim Schulze
  • Patent number: 8872264
    Abstract: A semiconductor device includes a first trench and a second trench extending into a semiconductor body from a surface. A body region of a first conductivity type adjoins a first sidewall of the first trench and a first sidewall of the second trench, the body region including a channel portion adjoining to a source structure and being configured to be controlled in its conductivity by a gate structure. The channel portion is formed at the first sidewall of the second trench and is not formed at the first sidewall of the first trench. An electrically floating semiconductor zone of the first conductivity type adjoins the first trench and has a bottom side located deeper within the semiconductor body than the bottom side of the body region.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: October 28, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Frank Pfirsch, Maria Cotorogea, Franz Hirler, Franz-Josef Niedernostheide, Thomas Raker, Hans-Joachim Schulze, Hans Peter Felsl
  • Patent number: 8860025
    Abstract: A semiconductor device includes a semiconductor diode. The semiconductor diode includes a drift region and a first semiconductor region of a first conductivity type formed in or on the drift region. The first semiconductor region is electrically coupled to a first terminal via a first surface of a semiconductor body. The semiconductor diode includes a channel region of a second conductivity type electrically coupled to the first terminal, wherein a bottom of the channel region adjoins the first semiconductor region. A first side of the channel region adjoins the first semiconductor region.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: October 14, 2014
    Assignee: Infineon Technologies AG
    Inventors: Anton Mauder, Franz Hirler, Hans-Peter Felsl, Hans-Joachim Schulze
  • Patent number: 8853774
    Abstract: A semiconductor device includes a first transistor cell including a first gate electrode in a first trench. The semiconductor device further includes a second transistor cell including a second gate electrode in a second trench, wherein the first and second gate electrodes are electrically connected. The semiconductor device further includes a third trench between the first and second trenches, wherein the third trench extends deeper into a semiconductor body from a first side of the semiconductor body than the first and second trenches. The semiconductor device further includes a dielectric in the third trench covering a bottom side and walls of the third trench.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: October 7, 2014
    Assignee: Infineon Technologies AG
    Inventors: Maria Cotorogea, Hans Peter Felsl, Yvonne Gawlina, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze, Georg Seibert, Andre Rainer Stegner, Wolfgang Wagner