Abstract: A monofacial or bifacial crystalline solar cell, on the front face of which over the entire area a first surface passivation layer is arranged directly on the semiconductor interface and above this a first optically opaque, electrically conductive material is arranged in first lateral regions as a front face contact, and a first optically transparent, electrically conductive material is arranged exclusively in second lateral regions. The first optically transparent, electrically conductive material is electrically conductively connected to the front face contact and to a first region of the semiconductor material of the solar cell. The method provides for application of the first optically transparent, electrically conductive material only after the first optically opaque, electrically conductive material has been applied, in such a way that firing of the front face contact is avoided.

Abstract: A solar cell with a heterojunction is produced. A first amorphous nano- and/or microcrystalline semiconductor layer is formed on the front face of a crystalline semiconductor substrate to form front face emitter or a front face surface field layer. A second such layer is formed on the rear face of the substrate to form a rear face surface field layer or a rear face emitter. Electrically conductive, transparent front face and rear face electrode layers and a frontal metallic contact layer grid structure are formed. Surface selective frontal PECVD deposition forms an electrically non-conductive, transparent dielectric front face cover layer and with such a thickness to form a closed layer directly on deposition, without additional heat and/or chemical treatment, only on the areas surrounding the frontal contact layer grid structure but not on the frontal contact layer grid structure. Finally, a rear face metallization is formed.

Abstract: A monofacial or bifacial crystalline solar cell, on the front face of which over the entire area a first surface passivation layer is arranged directly on the semiconductor interface and above this a first optically opaque, electrically conductive material is arranged in first lateral regions as a front face contact, and a first optically transparent, electrically conductive material is arranged exclusively in second lateral regions. The first optically transparent, electrically conductive material is electrically conductively connected to the front face contact and to a first region of the semiconductor material of the solar cell. The method provides for application of the first optically transparent, electrically conductive material only after the first optically opaque, electrically conductive material has been applied, in such a way that firing of the front face contact is avoided.

Abstract: A solar cell with a heterojunction is produced. A first amorphous nano- and/or microcrystalline semiconductor layer is formed on the front face of a crystalline semiconductor substrate to form front face emitter or a front face surface field layer. A second such layer is formed on the rear face of the substrate to form a rear face surface field layer or a rear face emitter. Electrically conductive, transparent front face and rear face electrode layers and a frontal metallic contact layer grid structure are formed. Surface selective frontal PECVD deposition forms an electrically non-conductive, transparent dielectric front face cover layer and with such a thickness to form a closed layer directly on deposition, without additional heat and/or chemical treatment, only on the areas surrounding the frontal contact layer grid structure but not on the frontal contact layer grid structure. Finally, a rear face metallization is formed.

Abstract: An integrated circuit device includes a substrate with a first layer situated on the substrate. The first layer defines a first opening with a cover layer deposited on the first layer and coating a sidewall portion of the first opening. A second layer is situated on the cover layer. The second layer defines a second opening extending through the second layer and through the cover layer to connect the first and second openings.

Abstract: A method for producing a layer stack includes providing a tungsten layer, depositing an oxidation barrier layer that immunizes the tungsten layer against oxidation on top of the tungsten layer, and depositing a cap layer on top of the oxidation barrier layer. An integrated circuit is also described.

Abstract: An integrated circuit device includes a substrate with a first layer situated on the substrate. The first layer defines a first opening with a cover layer deposited on the first layer and coating a sidewall portion of the first opening. A second layer is situated on the cover layer. The second layer defines a second opening extending through the second layer and through the cover layer to connect the first and second openings.

Abstract: The present invention relates to a method of forming a carbon layer on a substrate. A substrate with a structured surface is provided, the structured surface comprising a sidewall. A plasma is formed from an atmosphere comprising a gaseous hydrocarbon compound. The substrate is processed with the plasma, thereby depositing a carbon layer on the structured surface of the substrate. According to one aspect of the invention, the gaseous hydrocarbon compound comprises a ratio of less than 2:1 between hydrogen and carbon. According to another aspect of the invention, the atmosphere comprises a gaseous additive compound, the gaseous additive compound having an affinity for binding to hydrogen. Accordingly, the plasma comprises a reduced reactive hydrogen content, thus enabling an improved carbon deposition at the sidewall of the structured surface.

Abstract: A method of forming a wiring level and an electrical isolation associated with the wiring level on a surface of a semiconductor wafer comprises the steps of providing the semiconductor wafer having said surface, forming a plurality of electrically conductive wiring lines upon said surface, each of the wiring lines having a spacing with respect to neighboring one of the wiring lines, depositing a first layer of amorphous carbon upon the wiring lines by means of non-conformal plasma enhanced chemical vapor deposition (PECVD), such that air-filled voids formed below the first layer within the spacings between neighboring wiring lines. Alternatively, OSG (organo-silicon glass) or FSG (fluorine doped silicon glass) may be deposited to yield air-filled voids within the spacings. According to an embodiment, the carbon, OSG or FSG layers are used as an IMD-layer (line-to-line isolation), added by a further layer of a dielectric material, which then serves as an ILD-layer (level-to-level isolation).

Abstract: The present invention relates to a method of fabricating a groove-like structure in a semiconductor device including etching a trench in a substrate, filling the trench with a spin-on-glass liquid forming a spin-on-glass liquid layer containing a solvent, baking the spin-on-glass liquid layer in order to remove the solvent and forming a baked layer, etching the baked layer to a predetermined depth using an etchant that provides a larger etch rate with regard to silicon than with regard to silicon nitride or silicon oxide, and, after etching the baked layer, annealing the remaining baked layer and forming a spin-on-glass oxide layer inside the trench.

Abstract: The present invention provides a fabrication method for a semiconductor structure having the steps of providing a semiconductor substrate (1); providing and patterning a silicon nitride layer (3) on the semiconductor substrate (1) as topmost layer of a trench etching mask; forming a trench (5) in a first etching step by means of the trench etching mask; conformally depositing a liner layer (10) made of silicon oxide above the resulting structure, which leaves a gap (SP) reaching into the depth in the trench (5); carrying out a V plasma etching step for forming a V profile of the line layer (10) in the trench (5); wherein the liner layer (10) is pulled back to below the top side of the silicon nitride layer (3); an etching gas mixture comprises C5F8, O2 and an inert gas is used in the V plasma etching step; the ratio (V) of C5F8/O2 lies between 2.5 and 3.5; and the selectivity of the V plasma etching step between silicon oxide and silicon nitride is at least 10.

Abstract: A method of forming a wiring level and an electrical isolation associated with the wiring level on a surface of a semiconductor wafer comprises the steps of providing the semiconductor wafer having said surface, forming a plurality of electrically conductive wiring lines upon said surface, each of the wiring lines having a spacing with respect to neighboring one of the wiring lines, depositing a first layer of amorphous carbon upon the wiring lines by means of non-conformal plasma enhanced chemical vapor deposition (PECVD), such that air-filled voids formed below the first layer within the spacings between neighboring wiring lines. Alternatively, OSG (organo-silicon glass) or FSG (fluorine doped silicon glass) may be deposited to yield air-filled voids within the spacings. According to an embodiment, the carbon, OSG or FSG layers are used as an IMD-layer (line-to-line isolation), added by a further layer of a dielectric material, which then serves as an ILD-layer (level-to-level isolation).

Abstract: The present invention provides a fabrication method for a semiconductor structure having the steps of providing a semiconductor substrate (1); providing and patterning a silicon nitride layer (3) on the semiconductor substrate (1) as topmost layer of a trench etching mask; forming a trench (5) in a first etching step by means of the trench etching mask; conformally depositing a liner layer (10) made of silicon oxide above the resulting structure, which leaves a gap (SP) reaching into the depth in the trench (5); carrying out a V plasma etching step for forming a V profile of the line layer (10) in the trench (5); wherein the liner layer (10) is pulled back to below the top side of the silicon nitride layer (3); an etching gas mixture comprises C5F8, O2 and an inert gas is used in the V plasma etching step; the ratio (V) of C5F8/O2 lies between 2.5 and 3.5; and the selectivity of the V plasma etching step between silicon oxide and silicon nitride is at least 10.

Abstract: A method for structuring metal is disclosed. At least one corrosion-intensive metal layer is deposited on an Si substrate by means of deposition method. An etching mask is then produced on the corrosion-intensive metal layer by photolithographic patterning processes using a resist. The metal layer can then be patterned through the etching mask by means of etching, preferably by plasma etching.

Abstract: A method for the shrink-hole-free filling of trenches in semiconductor circuits which utilizes selective growth of a layer to be applied is described. In the method, a layer of a selective growing material is applied simultaneously to a growth-promoting layer and to a growth-inhibiting layer. Wherein raised portions which, before the layer of selective growing material is applied, are covered by the growth-inhibiting layer at least on their sides. After the growth-inhibiting layer has been applied, the growth-promoting layer is generated by anisotropic treatment on surfaces parallel to the substrate on and between the raised portions and the layer is then removed again on surfaces parallel to the substrate on the raised portions. The method makes it possible to produce in a particularly simple manner a pattern on the raised portions of which are covered by the growth-inhibiting layer on their sides and on their top whereas the bottom of trenches is covered with a growth-promoting layer.

Abstract: A method for the treatment of objects, preferably wafers, in a corresponding apparatus. The apparatus having at least two or more process chambers for receiving and treating the objects as well as a handling apparatus, for example a robot arm, for loading and unloading the process chambers. To date, all the process chambers have been loaded with the objects directly in succession. Accordingly, the actual treatment begins virtually simultaneously in all the process chambers. Furthermore, the necessary cleaning processes in the process chambers are also carried out virtually simultaneously.

Abstract: The fabrication method provides for an etched isolation trench to be lined, if appropriate firstly with a thin thermal oxide layer, and then with an oxidizable auxiliary layer. The auxiliary layer consumes oxygen during subsequent thermal processes, thereby avoiding oxidation of deeper structures, in particular of an insulation collar in a capacitor trench.

Abstract: An antireflection layer, preferably a dielectric antireflection layer, is applied by PECVD to a hard mask layer which is composed of doped silicon oxide, with no interruption of the vacuum. The silicon oxide layer is then patterned to form a hard mask and, by way of example, a deep trench etching is performed. The hard mask is removed using an HF/H2SO4 mixture or using an HF/ethylene glycol (EG) mixture at a high etching rate. If the HF/EG mixture is used, an intermediate layer that may be disposed underneath can simultaneously be etched back by a predetermined amount. The integration of two wet etching steps constitutes a major simplification compared with the previous wet etching methods in two different installations.