Patents by Inventor HANS RAJ SINGH

HANS RAJ SINGH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11945840
    Abstract: The present invention relates to novel protein pores and their uses in analyte detection and characterisation. The invention particularly relates to an isolated pore complex formed by a CsgG-like pore and a modified CsgF peptide, or a homologue or mutant thereof, thereby incorporating an additional channel constriction or reader head in the nanopore. The invention further relates to a transmembrane pore complex and methods for production of the pore complex and for use in molecular sensing and nucleic acid sequencing applications.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: April 2, 2024
    Assignees: VIB VZW, Vrije Universiteit Brussel, Oxford Nanopore Technologies PLC
    Inventors: Han Remaut, Sander Van Der Verren, Nani Van Gerven, Lakmal Jayasinghe, Elizabeth Jayne Wallace, Pratik Raj Singh, Richard George Hambley, Michael Jordan, John Joseph Kilgour
  • Patent number: 8645892
    Abstract: An integrated circuit (IC) design includes configurable circuits arranged in a mesh structure to facilitate routing of signals between different platforms or logic blocks within the design. Each configurable circuit has a semiconductor element with input and output terminals in a first semiconductor layer, input/output (I/O) ports corresponding to directions of the mesh structure in a second semiconductor layer, configurable input vias to allow a signal traveling in a first direction to be received, and configurable output vias that allow an output signal to be output from the configurable circuit in a second direction.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: February 4, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Vishal Gupta, Puneet Dodeja, Hans Raj Singh
  • Publication number: 20130080990
    Abstract: A method and system for performing power leakage reduction for an integrated circuit (IC) in a Virtual Multi-mode Multi-corner set up. Multiple view of the IC design data are analyzed in parallel to determine which low threshold voltage cells (LTVC) may be replaced with high threshold voltage cells (HVTC). A second analysis is performed that combines the analyses of each of the analyzed views and the IC design data is updated, where all of the LTVCs having positive slack time in all of the plurality of views are replaced with HTVCs.
    Type: Application
    Filed: September 27, 2011
    Publication date: March 28, 2013
    Applicant: FREESCALE SEMICONDUCTOR, INC
    Inventor: HANS RAJ SINGH