Patents by Inventor Hans Schlenker

Hans Schlenker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240308759
    Abstract: Workpiece storage device having at least one sensor; a control device; and pick-up device with receptacles individually adapted to shapes of workpieces to be received in the receptacles. The at least one sensor is configured to acquire sensor data to determine the presence and/or location of workpieces in the receptacles, and to transmit the sensor data to the control device. The control device is configured to receive the sensor data of the sensor and to feed the received sensor data as input values to at least one machine learning model, and the machine learning model is trained to calculate at least one binary output value from the input values. The at least one binary output value is indicative of whether a statement about a loading state of the pick-up device is applicable, and the control device is configured to generate a signal including the at least one binary output value.
    Type: Application
    Filed: May 20, 2024
    Publication date: September 19, 2024
    Applicant: Hoffmann Engineering Services GmbH
    Inventors: Hans SCHLENKER, Ritavan, Katrin SCHINDLER, Thomas MÜLTNER
  • Patent number: 9256430
    Abstract: A processor instruction scheduler comprising an optimization engine which uses an optimization model for a processor architecture with: means to generate an optimization model for the optimization engine from a design of a processor and data representing optimization goals and constraints and a code stream, wherein the processor has at least two execution pipes and at least two registers, and wherein the code stream comprises processor instructions with corresponding register selections; and reordering means to generate an optimized code stream from the code stream with the optimal solution provided by the optimization engine for the optimization model by reordering the code stream, such that optimum values for the optimization goals under the given constraints are achieved without affecting the operation results of the code stream.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: February 9, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Juergen Koehl, Jens Leenstra, Philipp Panitz, Hans Schlenker
  • Publication number: 20150127926
    Abstract: A processor instruction scheduler comprising an optimization engine which uses an optimization model for a processor architecture with: means to generate an optimization model for the optimization engine from a design of a processor and data representing optimization goals and constraints and a code stream, wherein the processor has at least two execution pipes and at least two registers, and wherein the code stream comprises processor instructions with corresponding register selections; and reordering means to generate an optimized code stream from the code stream with the optimal solution provided by the optimization engine for the optimization model by reordering the code stream, such that optimum values for the optimization goals under the given constraints are achieved without affecting the operation results of the code stream.
    Type: Application
    Filed: January 8, 2015
    Publication date: May 7, 2015
    Inventors: Juergen KOEHL, Jens LEENSTRA, Philipp PANITZ, Hans SCHLENKER
  • Patent number: 8972961
    Abstract: A processor instruction scheduler comprising an optimization engine which uses an optimization model for a processor architecture with: means to generate an optimization model for the optimization engine from a design of a processor and data representing optimization goals and constraints and a code stream, wherein the processor has at least two execution pipes and at least two registers, and wherein the design comprises data for processor instruction latency and execution pipes, and wherein the code stream comprises processor instructions with corresponding register selections; and reordering means to generate an optimized code stream from the code stream with the optimal solution provided by the optimization engine for the optimization model by reordering the code stream, such that optimum values for the optimization goals under the given constraints are achieved without affecting the operation results of the code stream.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Juergen Koehl, Jens Leenstra, Philipp Panitz, Hans Schlenker
  • Patent number: 8935685
    Abstract: A processor instruction scheduler comprising an optimization engine which uses an optimization model for a processor architecture with: means to generate an optimization model for the optimization engine from a design of a processor and data representing optimization goals and constraints and a code stream, wherein the processor has at least two execution pipes and at least two registers, and wherein the design comprises data for processor instruction latency and execution pipes, and wherein the code stream comprises processor instructions with corresponding register selections; and reordering means to generate an optimized code stream from the code stream with the optimal solution provided by the optimization engine for the optimization model by reordering the code stream, such that optimum values for the optimization goals under the given constraints are achieved without affecting the operation results of the code stream.
    Type: Grant
    Filed: April 28, 2012
    Date of Patent: January 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Juergen Koehl, Jens Leenstra, Philipp Panitz, Hans Schlenker
  • Publication number: 20120216016
    Abstract: A processor instruction scheduler comprising an optimization engine which uses an optimization model for a processor architecture with: means to generate an optimization model for the optimization engine from a design of a processor and data representing optimization goals and constraints and a code stream, wherein the processor has at least two execution pipes and at least two registers, and wherein the design comprises data for processor instruction latency and execution pipes, and wherein the code stream comprises processor instructions with corresponding register selections; and reordering means to generate an optimized code stream from the code stream with the optimal solution provided by the optimization engine for the optimization model by reordering the code stream, such that optimum values for the optimization goals under the given constraints are achieved without affecting the operation results of the code stream.
    Type: Application
    Filed: April 28, 2012
    Publication date: August 23, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Juergen Koehl, Jens Leenstra, Philipp Panitz, Hans Schlenker
  • Publication number: 20110289297
    Abstract: A processor instruction scheduler comprising an optimization engine which uses an optimization model for a processor architecture with: means to generate an optimization model for the optimization engine from a design of a processor and data representing optimization goals and constraints and a code stream, wherein the processor has at least two execution pipes and at least two registers, and wherein the design comprises data for processor instruction latency and execution pipes, and wherein the code stream comprises processor instructions with corresponding register selections; and reordering means to generate an optimized code stream from the code stream with the optimal solution provided by the optimization engine for the optimization model by reordering the code stream, such that optimum values for the optimization goals under the given constraints are achieved without affecting the operation results of the code stream.
    Type: Application
    Filed: May 11, 2011
    Publication date: November 24, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Juergen Koehl, Jens Leenstra, Philipp Panitz, Hans Schlenker