Abstract: A video display unit includes a built-in switched mode power supply and control means, responsive to the presence of one or more active sync signals (Hsync, Vsync), to switch on the display unit from the DPMS OFF mode, in which it consumes a minimum amount of power and to which it is switched in the absence of any active sync signal. Peak sensing circuitry detects that at least one sync signal is active, when switch is closed. A switch disconnects the SMPS controller from the start-up power source until the optocoupler is driven.

Abstract: A buffer circuit for use between a two-way open-collector bus line and a device capable of reading the status of the bus line and driving it low. The device has a single input/output terminal to which is connected a line of the buffer circuit. The buffer circuit is such as to distinguish between three logical levels on the line, and in particular between two logical low levels (U.sub.a, U.sub.b), which correspond to the device or an input buffer driving the bus line low. The input and output buffers are comprised by respective comparators. The reference voltage for the output buffer comparator lies between U.sub.a and U.sub.b, whereby to achieve the distinction therebetween. When the output buffer comparator detects U.sub.a, it causes the bus line to be driven low.