Abstract: A method is provided for material-removing machining when moving a tool of a machine tool along a tool path, including providing a workpiece comprising a first workpiece portion and a second workpiece portion adjacent to the first workpiece portion, wherein the tool path comprises a first path section comprising path segments adapted to a geometry of the first workpiece portion, and a second path section comprising path segments adapted to a geometry of the second workpiece portion. The method comprises determining the first path section to cover the first workpiece portion except for a first edge section, determining the second path section to cover the second workpiece portion except for a second edge section, and determining a transition section of the tool path to cover the first edge section and the second edge section, such that the first and second path sections and the transition section cover the entire first and second workpiece portions.

Abstract: A method for analyzing an integrated circuit (or constituent parts thereof), a computer program implementing the method, and a computer configured to execute the program is disclosed. Analyzing the integrated circuit may include retrieving a design for the integrated circuit from a layout database, identifying the bond pads and gates included in the design of the integrated circuit, determining the connections between the bond pads and the gates, and determining whether a connection between a particular gate and a particular bond pad lacks a connection segment routed over a required layer.

Abstract: The novel apparatus permits precise measurements of parasitic capacitances. The apparatus has a test structure and a reference structure, each with two conductor tracks. In the reference structure, the two conductor tracks are always at the same potential. In the test structure, one conductor track is coupled to ground potential and the other conductor track to a different potential. The test structure and the reference structure are connected to a voltage potential and the charge which builds up on the test structure and the reference structure is registered. The parasitic capacitance can be calculated precisely from the charge difference. The conductors of the test structure and of the reference structure are arranged in such a way that each conductor perceives a relationship to capacitive parasitic effects in the same environment.

Abstract: An electrical circuit can be described by a layout and by a network list. A network list has one or more cells each having one or more cell entities. From an existing layout, intrinsic capacitance values and coupling capacitance values of the networks are determined for all of the cell entities. Using these capacitance values, the cell entities are classified into variants. These variants are used in the simulation of the behavior of the electrical circuit.

Abstract: An electrical circuit can be described by a layout and by a network list. A network list has one or more cells each having one or more cell entities. From an existing layout, intrinsic capacitance values and coupling capacitance values of the networks are determined for all of the cell entities. Using these capacitance values, the cell entities are classified into variants. These variants are used in the simulation of the behavior of the electrical circuit.

Abstract: The novel apparatus permits precise measurements of parasitic capacitances. The apparatus has a test structure and a reference structure, each with two conductor tracks. In the reference structure, the two conductor tracks are always at the same potential. In the test structure, one conductor track is coupled to ground potential and the other conductor track to a different potential. The test structure and the reference structure are connected to a voltage potential and the charge which builds up on the test structure and the reference structure is registered. The parasitic capacitance can be calculated precisely from the charge difference. The conductors of the test structure and of the reference structure are arranged in such a way that each conductor perceives a relationship to capacitive parasitic effects in the same environment.